View 1991245_330585.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
PM5316/PM5310
SPECTRA-4X155 WITH TBS
REFERENCE DESIGN
PRELIMINARY ISSUE 1: JUNE 2000
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
PUBLIC REVISION HISTORY Issue No. 1 Issue Date Details of Change
June 2000 Document created.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
CONTENTS 1 2 3 4 5 6 7 DEFINITIONS .......................................................................................... 1 FEATURES .............................................................................................. 2 APPLICATIONS ....................................................................................... 3 REFERENCES......................................................................................... 4 APPLICATION EXAMPLES ..................................................................... 5 BLOCK DIAGRAM ................................................................................... 6 FUNCTIONAL DESCRIPTION................................................................. 7 7.1 7.2 7.3 7.4 7.5 7.6 PM5316 SPECTRA-4X155 ........................................................... 7 PM5310 TBS ................................................................................. 8 PLX TECHNOLOGY 9054 PCI INTERFACE................................. 8 CPLD............................................................................................. 9 CLOCKS...................................................................................... 10 POWER SUPPLY.........................................................................11 7.6.1 VOLTAGE REGULATORS ................................................11 7.6.2 HOT SWAP CONTROLLER ..............................................11 7.7 8 SYSTEM INTERFACE ................................................................ 13
IMPLEMENTATION DESCRIPTION ...................................................... 15 8.1 8.2 8.3 8.4 8.5 ROOT DRAWING, PAGE 1 ......................................................... 15 OPTICS BLOCK, PAGE 2 ........................................................... 15 SPECTRA-4X155 BLOCK, PAGES 3,4,5,6 & 7 ......................... 15 TBS BLOCK, PAGES 8, 9,10, & 11............................................. 16 SYSTEM INTERFACE BLOCK, PAGE 12................................... 17
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
i
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
8.6 8.7 8.8 9 10
CPLD BLOCK, PAGE 13............................................................. 17 CPCI BLOCK, PAGES 14 & 15 ................................................... 18 POWER BLOCK, PAGE 16......................................................... 18
SCHEMATICS AND LAYOUT ................................................................ 20 BILL OF MATERIAL ............................................................................... 21
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
ii
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
LIST OF FIGURES
FIGURE 1 - ADD/DROP MUX. .......................................................................... 5 FIGURE 2 - SPECTRA-4X155 REFERENCE DESIGN BOARD....................... 6 FIGURE 3 - CPLD FUNCTIONAL BLOCK DIAGRAM..................................... 10 FIGURE 4 - POWER SUPPLY SYSTEM BLOCK. ...........................................11 FIGURE 5 - CPCI HOT SWAP CIRCUIT......................................................... 12
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
iii
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
LIST OF TABLES
TABLE 1 TABLE 2 TABLE 3
- WORKING AND PROTECT HS3 CONNECTOR PINOUT .......... 13 - AUXILIARY HS3 CONNECTOR PINOUT .................................... 14 - BILL OF MATERIAL..................................................................... 21
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
iv
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
1
DEFINITIONS LOS Loss of signal - When a SONET receiver detects and allzeros pattern for 10 microseconds or longer, this constitutes a LOS failure. It indicates that the upstream transmitter has failed. This condition is cleared when two consecutive valid frames are received. Loss of frame - The absense of valid framing pattern for 3 microseconds leads to a LOF failure condition. This is cleared when two consecutive valid A1/A2 framing patterns are received. Optical Data Link ElectroStatic Discharge Alarm indication signal - This condition can occur in response to one of the conditions above. The SONET signal format provides AISs for the line (AIS-L), STS Path (AIS-P), and VT Path (AIS-V) layers. Bit Error Rate Clock Recovery Unit - Recovers timing information from receive data streams. Clock Synthesis Unit - Generates timing signal for transmit data streams.
LOF
ODL ESD AIS
BER CRU CSU
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
1
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
2
FEATURES * * * * * * * 33 MHz CompactPCI (cPCI) interface. 4 HP MT-RJ OC-3 rate line side transceivers operating at 3.3V provide 622 Mbit/s aggregate operation. 3.3 V CMOS ADD/DROP Telecom bus interface to the TBS ADD/DROP Telecom bus interface. Telecom bus is configured to operate in single STS-12 (STM-4) mode at 77.76 MHz. CPLD performs address decoding, timing source selection and signal interfacing functions. Line interface speeds up to 155.52 Mbit/s. Enables 4XOC-3 channelization.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
2
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
3 * * *
APPLICATIONS SONET/SDH Multiservice ADMs SONET/SDH Cross Connects SONET/SDH Terminal Multiplexers
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
3
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
4
REFERENCES
1. PMC-Sierra, Inc. PMC-990822, "SPECTRA-4X155 Data Sheet ", March 2000, Issue 1. 2. PMC-Sierra, Inc. PMC-990522, "TBS Telecombus Serializer", May 1999, Issue 1. 3. PLX Technology, Inc. , "PCI 9054 Data Book v2.0", August 1999.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
4
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
5
APPLICATION EXAMPLES The SPECTRA-4X155 WITH TBS Reference Card can be implemented as a multi-service ADM in a SONET network. Four line side OC-3 channels provide considerable flexibility for implementing SONET ring architectures. Figure 1 below outlines a typical ADM application. Figure 1 - Add/Drop MUX.
SPECTRA-155 QUAD WITH TBS Line Card
DROP RING RING ADD
OC-N
OC-N
OC-M
OC-M
ADD/DROP Bus
DROP
RING
RING
ADD
OC-N
SPECTRA-155 QUAD WITH TBS Line Card
OC-N
The SPECTRA-4X155 WITH TBS Line Card can also be implemented as a SONET/SDH digital cross connect. Two TBS devices on two line cards can be interfaced to create a simple switch architecture. Note that the TBS can switch at STS-1 granularity only in the parallel to serial or serial to parallel directions. A more complete digital cross-connect can be implemented utilizing the TSE as the core cross-connect element. Additionally, the Line Card can be implemented as a Terminal Multiplexer, which is similar to the ADM, except that all incoming traffic to the card is dropped. This application would allow all four OC-3 streams to be terminated in a point-to-point network.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
5
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
6
BLOCK DIAGRAM Figure 2 - SPECTRA-4x155 Reference Design Board
MT-RJ MT-RJ MT-RJ MT-RJ
DD DC1J1V1 DPL DDP AD AC1J1V1/AFP APL ADP
8 4 4 4 8 4 4 4
ID IJ0J1 IPL IDP OD PM5310 OJ0J1 OPL ODP SYSCLK ADDR DATA CSB 12 16
TBS
PM5316 SPECTRA-155 QUAD ACK
TPWRK TNWRK TPPROT TNPROT RPWRK RNWRK RPPROT RNPROT RJ0FP TJ0FP RWSEL xCMP
4 4 4 4 4 4 4 4
AMP HS3 60 PIN
DCK CSB
SYSCLK
CPLD
19.44 MHz Ref Clk
77.76 MHz Osc.
REFCLK ADDR DATA 14 8
SMA
PLX 9054 PCI BRIDGE
CPCI 32 32
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
6
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
7
FUNCTIONAL DESCRIPTION The PM5316 SPECTRA-4X155 receives 4 OC-3 SONET/SDH serial bit streams from 4 Hewlett Packard MT-RJ optical transceivers and recovers clock and data. The chip processes SONET section, line, and path overhead. The 77.76 Mbit/s Telecom ADD/DROP bus on the SPECTRA-4X155 connects directly to the Telecom ADD/DROP bus on the TBS. The extracted payload from the incoming data bit stream is placed on the DROP Telecom bus and routed to the TBS in byte-serial format. The TBS receives and serializes the incoming byte-serial data stream into a bit-serial stream. The bit-serial stream is routed to the backplane via a pair of working, a pair of auxiliary, and a pair of protect 777.6 MHz LVDS serial links with 8B/10B-based encoding. The system side of the SPECTRA-4X155 device is configured to operate in single DROP/ADD Telecombus mode at 77.76 MHz. In this mode, a single STS12 byte-serial stream connects to the Telecom bus interface of the TBS device and only the lower 8 bits of the TBS's 32 bit parallel Telecombus are required to pass traffic. The reference board routes signals to and from a backplane which permits further processing by other members of the CHESS chipset. For example, the S/UNI MACH48 is used to terminate ATM or bit/byte HDLC. The system clock source is selectable between two modes. The board can provide it's own system clock via an onboard 77.76 MHz oscillator, or it can receive the clock signal through the backplane from a timing card. The SPECTRA-4X155 19.44 MHz reference clock is provided by an on board oscillator.
7.1
PM5316 SPECTRA-4X155 The PM5316 SPECTRA-4X155 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER terminates the transport and path overhead of four STS-3 155 Mbit/s streams. The SPECTRA-4X155 receives SONET/SDH frames via bit serial interfaces, recovers clock and data, and terminates the SONET/SDH section, line, and path. The SPECTRA-4X155 performs framing (A1,A2), descrambling, detects alarm conditions, and monitors section and line bit interleaved parity (BIP) (B1, B2), accumulating error counts at each level for performance monitoring purposes. The SPECTRA-4X155 interprets the received payload pointers (H1, H2) and extracts the synchronous payload envelope (virtual container).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
7
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
The SPECTRA-4X155 transmits SONET/SDH frames, via bit serial interfaces. The chip performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, and creates section and line BIPs (B1, B2) as required to allow performance monitoring at the far end. In addition to its basic processing of the transmit SONET/SDH overhead, the SPECTRA-4X155 provides convenient access to all overhead bytes, which are inserted serially on lower rate interfaces, allowing additional external sourcing of overhead, if desired. The SPECTRA-4X155 is implemented in 3.3V, CMOS process technology. It has TTL and positive ECL (PECL) compatible inputs and outputs. The SPECTRA-4X155 is configured, controlled and monitored via a generic 8-bit microprocessor bus interface and has a standard 5 signal JTAG test port for boundary scan board test purposes. The SPECTRA-4X155 is available in a 520 pin SBGA package. 7.2 PM5310 TBS The PM5310 TBS Telecom bus serializer is a monolithic integrated circuit that implements conversions between parallel Telecom bus and the serial Telecom bus. The TBS can be used to connect SONET/SDH framer devices to ATM/POS processor devices or to cross-connect devices. The TBS can also be used to connect cross-connect devices (like the PM5372 TSE) to SONET/SDH tributary unit processors and PDH mapper devices. The TBS connects the Parallel-Telecom Bus to three sets of four serial LVDS links called Working, Protect and Auxiliary. Transport and payload frame boundaries, pointer justification events and alarm conditions are marked with 8B/10B control characters. The read Working channel selection signal (RWSEL) determines which receive S-TCB port is forwarded to the outgoing P-TCB. Software control allows for mixing the data on the outgoing P-TCB from any of the three S-TCB ports. The TBS is configured, controlled and monitored via a generic 16-bit microprocessor bus interface and has a standard 5 signal JTAG test port for boundary scan board test purposes. The TBS is available in a 352 pin UBGA package. 7.3 PLX Technology 9054 PCI Interface The PLX Technology PCI9054 provides the interface between the system PCI signals and the local bus on the SPECTRA-4X155 Reference Design board. The system PCI signals are found on connector J1_1. The PCI9054 bridge provides data and address information on the local bus side, and interrupt signalling to the host processor card. The PCI9054 device is configured via a 1K-bit serial EEPROM device.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
8
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
7.4
CPLD The CPLD is used for chip select decoding for SPECTRA and TBS devices that share the LA[31..2] and LD[31..0] buses. The LA[16] and LA[17] bits are used to select the appropriate device to access. When LA[17] =1, the CPLD will have it's internal register accessed with the data on LD[0] and LD[1]. When LA[17] is 0, the RDB and WRB signals are passed and LA[16] bit is used to decode between the chip selects of the SPECTRA-4X155 and the TBS. LA[16] =0 will assert the CSB_SPECTRA signal, while LA[16] =1 asserts the CSB_TBS signal. The internal register is used to select the clock source for SYSCLK, DCK and ACK. LD[0] selects between the backplane supplied SYSCLK signal and the onboard oscillator. The CPLD is used to change the local read/write signal from the PCI controller (L_WRB) into two separate signals for the microprocessor interface signals RDB and WRB. The CPLD acts as a buffer for the non-LVDS signals that come in from the backplane and can show debugging information with 8 LEDs. Some of the overhead signals from the SPECTRA_4X155 are routed to the CPLD for debugging/overhead monitoring. Figure 3 details the functions of the CPLD.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
9
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
Figure 3
- CPLD Functional Block Diagram
L_ADSB L_WRB LHOLD LHOLDA L_READYB
RDB
Micro Interface Control
WRB LCLK
LA[17]
CSB_TBS
CSB_SPECTRA
LA[16]
Registers
LD[2:0]
LOCAL_OSC
Divide By N
SYSCLK SYSCLK1 SYSCLK2 INTB_SPECTRA INTB_TBS
INTB
7.5
Clocks The 77.76 MHz system clock signal for the TBS and ACK and DCK Telecom bus clocks for the SPECTRA-4X155 can be configured in two ways: from an onboard 77.76 MHz oscillator or from the backplane. The SPECTRA-4X155 19.44 MHz reference with a balance of 20 ppm is supplied by either a 19.44 MHz oscillator or optionally the reference clock can be supplied externally through a SMB connector.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
10
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
7.6
Power Supply Figure 4 - Power Supply System Block.
+5V +3.3V
+5V_PCI +3.3V_PCI +12V_PCI -12V_PCI GND BD_SEL# HEALTHY# PCI_RST#
Hot Swap Controller LT1643L
+12V -12V
+5V
Switching Regulator
1.8V
The Power Block provides stable voltage supplies delivered over the CompactPCI backplane from a centralized power supply. Voltage levels of +5V, +3.3V, +12V, -12V and regulated 1.8V are available from this block. 7.6.1 Voltage Regulators Linear regulators supply the 3.3V analog and 1.8V analog pins of the SPECTRA4X155 and TBS devices respectively. These regulators are located on the power sheets of the SPECTRA-4X155 and the TBS. The 5V to 1.8V switching regulator module is used to generate the supply labelled 1.8V. Only the TBS uses this supply. 7.6.2 Hot Swap Controller The Hot Swap Controller is used to allow the board to be safely inserted or removed from a live cPCI slot. External N-channel MOSFETS control the 3.3V and 5V supplies, while the +12V and -12V supplies are controlled with on-chip switches. The supply voltages are ramped up at a programmable rate. The hot swap controller is implemented using the Linear Technology LTC1643L. A typical cPCI Hot Swap circuit is shown below in Figure 2. Note that only the hot swap controller is implemented in the power block. Additional Hot Swap circuitry including the precharge circuitry for the cPCI bus is included in the CompactPCI block.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
11
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
Figure 5
- cPCI Hot Swap Circuit
0.01 Q1 IRF7413
+5V_PCI 0.005 +3.3V_PCI R1
Q1 IRF7413
R2 R4
5V 5A 3.3V 7.6A
10 100
R3 V(I/O) CompactPCI Connector R6 1.2k R7 2k
10
R5 3Vin 3Vsense GATE 3Vout 5Vin 5Vsense 5Vout 12Vin VEEin ON# V(I/O) FAULT# 12Vout VEEout 12V 500mA -12V 100mA
+12V_PCI -12V_PCI BD_SELB
LT1643L
12V HEALTHYB 0.1uF GND 0.1uF
R8 2k PWRGD# GND TIMER 0.01uF
The 3.3V, 5V, +12V, and -12V power supplies are generated from the medium length power pins on the PCI connector (+5V_PCI, +3.3V_PCI, etc). The long power pins which make the first connections are used to generate a 1V precharge voltage on the cPCI bus pins. In the circuit above, the 3.3V and 5V power supplies are controlled by the Nchannel pass transistors Q1 and Q2. Internal circuitry controls the +/-12V rails. R1 and R2 control overcurrent conditions. R5 and C1 provide current control loop compensation. R3 and R4 prevent high frequency oscillations in the pass transistors. Finally, the 12V Zener diode protects against power surges on the -12V rail. During an insertion and power-up sequence, the BD_SEL# pin is the final pin to connect to the board. This pin is connected to the ON# pin of the Hot Swap Controller. When the ON# pin is pulled low, the pass transistors are turned on by pulling the GATE pin high, and the current in each pass transistor rises at a rate of dv/dt = 50A/C1, until reaching the preset limit. If there is a high load capacitance, the rate of increase will be controlled by this value. Once the supply voltages stabilize the PWRGD# signal is pulled low. The sense resistors R1 and R2 in Figure 5 above set the current limit for the 5V and 3.3V supplies. The current limit is governed by the following equation:
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
12
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
I
lim
= 53mV / R sense
In the circuit of Figure 4 above, the 3.3V current limit will be 10.6A, and the 5V limit will be 5.3A. Upon removal, the /ON pin will be pulled high, and the GATE pin on the pass transistors is pulled low to prevent load currents on the 3.3V and 5V rails from instantaneously going to zero and glitching the power supply. The /PWRGD pin is pulled high if any of the supply voltages moves below its threshold. 7.7 System Interface This board is based on the cPCI 6U (233.35mm by 160mm) board size. The J1_1 connections are standard cPCI pinouts and the connector carries 32 standard cPCI signals. The other connectors implemented in this reference design are the AMP HS3 60 pin connectors. These connectors are used to connect the 777.6 Mbit/s LVDS signals and control signals to the backplane. Note that the columns of the connector are separated by ground planes. Column 10 of the HS3 connector does not have ground shielding on the outer side, therefore low speed signals are placed in this column. The pin assignments are made in the low-noise configuration as specified by AMP. The table on the following page outlines the HS3 pinout.
Table 1 Column 1 A
- Working and Protect HS3 Connector Pinout B SYSCLK1P RPPROT4 RPPROT3 RPPROT2 RPPROT1 RPWRK4 RPWRK3 C SYSCLK1N RNPROT4 RNPROT3 RNPROT2 RNPROT1 RNWRK4 RNWRK3 D SYSCLK2 P TPPROT4 TPPROT 3 TPPROT2 TPPROT1 TPWRK4 TPWRK3 E SYSCLK2N TNPROT4 TNPROT3 TNPROT2 TNPROT1 TNWRK4 TNWRK3 F GND GND GND GND GND GND GND
GND GND GND GND GND GND GND
2 3 4 5 6 7
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
13
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
Column 8 9 10-
A GND GND GND
B RPWRK2 RPWRK1 TJ0FP_OUT
C RNWRK2 RNWRK1 RJ0FP_IN
D TPWRK2 TPWRK1 RWSEL_I N
E TNWRK2 TNWRK1 XCMP_IN
F GND GND GND
Table 2 Column 1 2 3 4 5 6 7 8 9 10 A
- Auxiliary HS3 Connector Pinout B GND GND GND GND GND GND GND GND GND GND C GND GND GND GND GND GND GND GND GND GND D GND TNAUX4 TNAUX3 TNAUX2 TNAUX1 GND RNAUX4 RNAUX3 RNAUX2 RNAUX1 E GND TPAUX4 TPAUX3 TPAUX2 TPAUX1 GND RPAUX4 RPAUX3 RPAUX2 RPAUX1 F GND GND GND GND GND GND GND GND GND GND
GND GND GND GND GND GND GND GND GND GND
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
14
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
8
IMPLEMENTATION DESCRIPTION This section describes the hardware implementation of the SPECTRA-4X155 WITH TBS reference design. Each section references the schematics contained in Section 9.
8.1
Root Drawing, Page 1 This page shows the interconnection between the functional blocks of the design.
8.2
Optics Block, Page 2 Page 2 shows the optical interface of the reference design. Four HP HFCT5905E MT-RJ Duplex single mode transceivers are used to transmit and receiver four OC-3 optical streams. The HFCT-5905E is a 3.3 V PECL device in a 10-pin package. The PECL signals are connected to the SPECTRA-4X155 receive and transmit pins through 50 ohm controlled impedance lines. The receive and transmit lines are properly terminated at the SPECTRA-4X155 and transceiver devices. The 150 ohm resistors provide source terminations for the PECL outputs from the ODL and should be placed as close as possible to the ODL. The resistor and capacitor networks between the TXDP and TXDN lines provide biasing for the SPECTRA-4X155 PECL TX outputs and should also be placed close to the ODL.
8.3
Spectra-4x155 Block, Pages 3,4,5,6 & 7 The SPECTRA_4x155_BLOCK shows the SPECTRA-4X155 signals and power circuitry. Page 3 contains Block 1 of the SPECTRA-4X155 device. Block 1 contains the line side signals of the SPECTRA-4X155. The PECL receive lines have parallel termination resistors of 100 ohms. The transmit differential TTL outputs have series capacitors of 0.1 uF to remove any DC component of the output signal and the 158 ohm resistors are used to bring the signals to PECL signaling levels. 0.22 uF capacitors are used for the loop filter pins, CP and CN. The PECLV pin is pulled to ground to select 3.3 V optics. The REFCLK source must be a 19.44 MHz 20ppm clock signal. By means of header J4, the clock source can be selected between an on-board oscillator or from an external source via a SMB connector.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
15
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
Page 4 contains Blocks 2 and 3 of the SPECTRA-4X155 device. Blocks 2 and 3 of the SPECTRA-4X155 contain the ADD/DROP Telecom bus signals. The DROP bus data signals DROP_DATA[7:0] contain the STS-3/3c received SONET/SDH payload data of all four channels. The DROP bus data signals DROP_DATA[31:8] are left floating because no data will be delivered via these bits. Similarly, for single ADD bus interface, the ADD bus data signals ADD_DATA[7:0] contain the STS-3/3c SONET/SDH payload data to transmit on the four channels. The ADD bus data signals ADD_DATA[31:8] are pulled low to prevent noise triggering these signals as these inputs will not receive any data. Header J9 provides access to the TPAIS, TPAISCK, TPAISFP, DPAIS, DPAISCK, and DPAISFP signals. Page 5 contains Block 4 of the SPECTRA-4X155 device. Block 4 contains the microprocessor and JTAG signals. JTAG is not implemented in this design therefore the pins are pulled-up to maintain appropriate signal state. Page 6 contains Block 5 of the SPECTRA-4X155 device. Block 5 of the SPECTRA-4X155 device contains the transmit and receive overhead signals. All of the signals are routed to a 32X2 pin header for access. The four SALM signals are routed off-page to the CPLD for alarm indication. The transmit inputs are pulled-low to prevent noise triggering of the signals. The Ring Control signals are routed to a matched impedance connector for debugging. Page 7 contains Block 6 of the SPECTRA-4X155 device. Block 6 contains the power pins for the SPECTRA-4X155. 20 of the 48 digital power pins have 0.1 uF decoupling capacitors placed as close as possible to the pins as well as 10uF bulk capacitors. The receive and transmit analog power pins are filtered via RC filters to provide a clean 3.3 voltage to the pins. VBIAS pins (VBIAS<1..0>) are tied to the 3.3V supply via a 1K resistor since there are no 5V devices on the board. The 3.3V regulator shown on this page is also used to supply the optics. 8.4 TBS Block, Pages 8, 9,10, & 11 The TBS_BLOCK shows the TBS signals and power circuitry. Page 8 contains Block 1 of the TBS device. Block 1 shows the system side LVDS signals of the TBS. These signals are received from and transmitted to the backplane. The LVDS are differential signals and the transmission traces must be 50 ohm controlled impedance lines. The TCMP and OCMP (connection memory page) signals are buffered by the CPLD and sourced from the backplane. The SYSCLK is sourced from either an on-board 77.77 MHz oscillator or an external 77.76 MHz clock signal.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
16
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
Page 9 contains Blocks 2 and 3 of the TBS device. Blocks 2 and 3 contain the ADD/DROP Telecom bus signals which interface the TBS to the SPECTRA4X155. Because the SPECTRA-4X155 Telecom bus is configured to operate in single-drop mode, only OD1[7:0] and ID1[7:0] data bits are used. Outgoing (ADD) Telecom bus channels OD2 to OD4 are left unconnected as well as their respective ODP, OPL, OJ0J1, OPAIS, OTV5, OTPL, OTAIS, and OCOUT signals. The OPAIS, OTV5, OTPL, OTAIS, and OCOUT for channel one are routed to a header for access. Incoming (DROP) Telecom bus channels ID2 to ID4 are pulled low to prevent noise triggering the signals as well as their respective IDP, IPL, IJ0J1, IPAIS, ITV5, ITPL, and ITAIS signals. Signals IPAIS, ITV5, ITPL, and ITAIS for channel one are routed to a header for access. Page 10 contains Block 4 of the TBS device. Block 4 contains the microprocessor and JTAG signals. JTAG is not implemented in this design therefore the pins are pulled-up to maintain appropriate signal state. Page 11 contains Block 5 of the TBS device and a regulated 1.8V supply. Block 5 contains the power pins for the TBS. Both the 3.3 Volt and the 1.8 Volt supply rails are decoupled via 0.1 uF capacitors as well as 10uF bulk capacitors. The supply to the CSU_AVDH pin is passed through an RC filter to provide a clean voltage to the pin. The RES and RESK pins are externally attached via a 3.16K resistor. The 1.8V regulator shown on this page is used to supply the 1.8V analog pins on the TBS device. 8.5 System Interface Block, Page 12 The SYS_INTERFACE_BLOCK contains the AMP HS3 connectors for transfer of the LVDS signals between the backplane and the reference board. The transmit and receive differential pairs are grouped together on the connector. The top HS3 connector contains the LVDS working and protect differential signals. The differential SYSCLK signals generated on the TSE reference board are also sent through the top connector. The bottom connector is used strictly for the LVDS auxiliary channels. This connector is optional and can be populated depending on the application requirements. All of the LVDS signal traces and the differential SYSCLK traces are 50 ohm controlled impedance lines. 8.6 CPLD Block, Page 13 The CPLD_BLOCK shows the signal connections to and from the Xilinx XC9572XL CPLD. The CPLD is used for address decoding, microprocessor access control, signal conversion, signal buffering, and clock distribution. The PECL differential clock signals, SYSCLK1(P,N) and SYSCLK2(P,N), are translated into single-ended TTL signals using the Motorola MC100EPT23 device. A 77.76 MHz local oscillator signal is also input to the CPLD. Through
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
17
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
software control, the CPLD can select which of the clock sources is to be used and sends the selected signal to the Pericom 49FCT3807 clock driver device. The 49FCT3807 clock distributes the 77.76 MHz signal to the SYSCLK input on the TBS as well as to the DCK and ACK Telecom bus clocks on the SPECTRA4X155. The Maxim 811 power supply monitor device with reset provides manual reset capability with a push-button switch attached to the master reset input. The Motorola MC74HC244 driver/buffer chip is used to drive the Lumex LXH5147 LED arrays. The LED's can be programmed to display the status of alarms from the SPECTRA-4X155 device or to display information for debugging. The microprocessor interrupt lines are also routed to the LED's for device interrupt status. Header J1 provides an interface to the CPLD JTAG pins for programming the device. 8.7 cPCI Block, Pages 14 & 15 The CPCI_BLOCK shows the PLX 9054 signal and power circuitry connections. The PCI9054 is a 3.3V/5V compliant PCI v2.2 32-bit, 33MHz Bus Master Interface Controller, that provides flexible local bus configurations and Hot Swap capability. The 32 bit multiplexed address/data bus and associated control lines connect directly from the CPCI J1_1 connector to the PLC PCI9054 interface device. The bus and control lines are terminated with 10 ohm stub resistors that should be placed close to the J1_1 connector pins. The PCI 9054 operates with a 32-bit non-multiplexed bus (C-mode) on the local bus side. The lower two bits of the address lines are used for 16 or 8 bit byte access but are unused in this application. A serial EEPROM is required for device configuration after reset or at power-up. The Fairchild Semiconductor NM93CS46 serial EEPROM is used to program the 9054. 8.8 Power Block, Page 16 The POWER_BLOCK shows the power signal connections, the Hot-Swap Controller, and voltage regulator connections.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
18
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
The Power Supply System Block provides stable voltage supplies delivered over the CompactPCI backplane from a centralized power supply. Voltage levels of +5V, +3.3V, +12V, -12V and a regulated 1.8V are provided. A voltage regulator is provided in the Power Supply System Block. The 1.8V switching regulator generates the core digital power supply required for the TBS device. The 3.3V SPECTRA devices are powered directly from the digital sections of the hot swap controller.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
19
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
9
SCHEMATICS AND LAYOUT
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
20
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
PAGE 2 OPTICS_BLOCK
PAGES 3,4,5,6,7 SPECTRA_4X155_BLOCK PAGES 8,9,10,11 TBS_BLOCK SD1 RXD_P1 RXD_N1 TXD_P1 TXD_N1 SD2 RXD_P2 RXD_N2 TXD_P2 TXD_N2 SD3 RXD_P3 RXD_N3 TXD_P3 TXD_N3 SD4 RXD_P4 RXD_N4 TXD_P4 TXD_N4 RJ0FP_SPECTRA DROP_DATA<7..0> DPL DC1J1V1 DDP DCK RJ0FP DROP_DATA<7..0> DPL DC1J1V1 DDP DCK DROP_DATA<7..0> DPL DC1J1V1 DDP TAUX<8..1> RAUX<8..1> PAGE 12 SYS_INTERFACE_BLOCK TAUX<8..1> RAUX<8..1>
H
SD1 RXD_P1 RXD_N1 TXD_P1 TXD_N1 SD2 RXD_P2 RXD_N2 TXD_P2 TXD_N2 SD3 RXD_P3 RXD_N3 TXD_P3 TXD_N3 SD4 RXD_P4 RXD_N4 TXD_P4 TXD_N4
SD1 RXD_P1 RXD_N1 TXD_P1 TXD_N1
TAUX<8..1> RAUX<8..1> G
G
SD2 RXD_P2 RXD_N2 TXD_P2 TXD_N2
SD3 RXD_P3 RXD_N3 TXD_P3 TXD_N3
ADD_DATA<7..0> APL AC1J1V1_AFP ADP ACK
ADD_DATA<7..0> APL AC1J1V1_AFP ADP ACK
TWRK<8..1> ADD_DATA<7..0> APL AC1J1V1_AFP ADP RWRK<8..1>
TWRK<8..1> RWRK<8..1>
TWRK<8..1> RWRK<8..1>
TPROT<8..1> RPROT<8..1>
TPROT<8..1> RPROT<8..1>
TPROT<8..1> RPROT<8..1> SYSCLK1P SYSCLK1N SYSCLK2P F
RESETB SD4 RXD_P4 RXD_N4 TXD_P4 TXD_N4 RDB WRB CSB_SPECTRA INTB_SPECTRA
RESETB RDB WRB CSB_TBS INTB_TBS LD<31..0> LA<31..2> RJ0FP_TBS TJ0FP RWSEL OCMP TCMP SYSCLK RJ0FP_IN TJ0FP_OUT RWSEL_IN XCMP_IN
F
SYSCLK2N
SYSCLK
RJ0FP_IN TJ0FP_OUT RWSEL_IN XCMP_IN
E LD<31..0> LA<31..2> LD<31..0> LA<31..2> PAGE 13 CPLD_BLOCK SALM<4..1> OVERHEAD<18..1> OVERHEAD<18..1> SALM<4..1> INTB_SPECTRA CSB_SPECTRA RESETB RDB WRB ACK DCK CSB_TBS INTB_TBS TCMP OCMP RWSEL TJ0FP RJ0FP_TBS RJ0FP_SPECTRA RJ0FP_IN TJ0FP_OUT RWSEL_IN XCMP_IN SYSCLK SYSCLK1P SYSCLK1N SYSCLK2P SYSCLK2N LD<31..0> LA<31..2> LHOLD LHOLDA L_ADSB L_READYB L_WRB L_USERI L_USERO L_RSTOB L_INTB L_CLK LD<31..0> LA<31..2> LHOLD LHOLDA L_ADSB L_READYB L_WRB L_USERI L_USERO L_RSTOB L_INTB L_CLK
PAGES 14, 15 CPCI_BLOCK E LD<31..0> LA<31..2>
D
D
INTB_TBS CSB_TBS DCK ACK WRB RDB RESETB CSB_SPECTRA
C
INTB_SPECTRA SALM<4..1> OVERHEAD<18..1> PWROK_1_8V
LHOLD LHOLDA L_ADSB L_READYB L_WRB L_USERI L_USERO L_RSTOB L_INTB L_CLK PWROK_1_8V
C
PWROK_1_8V PAGE 16 POWER_BLOCK PWROK_1_8V B 5V_PCI 3_3V_PCI 12V_PCI VEE_PCI BD_SELB HEALTHYB VIO_PCI 5V_PCI 3_3V_PCI 12V_PCI VEE_PCI BD_SELB HEALTHYB VIO_PCI 5V_PCI 3_3V_PCI 12V_PCI VEE_PCI BD_SELB HEALTHYB VIO_PCI
B
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-991245 DOCUMENT ISSUE NUMBER: 1 DRAWING: TITLE=SPECTRA_4X155_ROOT LAST_MODIFIED=Thu Jun 15 09:37:04 2000 10 9 8 7 6 5 4 3 TITLE: SPECTRA 4X155 REFERENCE DESIGN ROOT_DIAGRAM ENGINEER: MB 2 ISSUE DATE: 00/06/09 REVISION NUMBER: 1 PAGE:1 1 OF 16 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H 3.3VA
100NH 0.01UF L1 0.01UF C71 10UF
H 3.3VA TXD_P1\I
100NH
3E8>
0.01UF L2 C72 10UF 0.01UF
TXD_P2\I
3F8>
+ 3.3VA
49.9 R46 0.1UF C2
C5
C67
C68
+
3.3VA
49.9 R47 0.1UF
C63
R35
C64
220
0.01UF
C75
C76
L5
0.01UF
L6
220
R37
100NH
100NH
G
G
330 49.9 R36
330
R34
6
2
49.9
U1
13 14 15 16 11 12
R42
U2 TXD_N1\I RXD_P1\I RXD_N1\I SD1\I
13 14 15 16 11 12
VCCT VCCR GND GND GND GND TXDP TXDN HFCT5905 RXDP RXDN SD TDIS VEER
1 9 10 5 4 3 8 R50 150
VCCT VCCR GND GND GND GND TXDP TXDN HFCT5905 RXDP RXDN SD TDIS VEER
1
3E8> 3E8< 3E8< 3E8<
9 10 5 4 3 8 R51 150 R55 150 150 R59
R43
6
2
TXD_N2\I RXD_P2\I RXD_N2\I SD2\I
3F8> 3E8< 3E8< 3E8<
CHASS1 CHASS2 VEET
7
CHASS1 CHASS2 VEET
7
R54 150
150
R58
F
F
3.3VA
100NH 0.01UF 0.01UF L3 C73
3.3VA
100NH 0.01UF L4 C74 0.01UF
TXD_P3\I
3F8>
10UF
TXD_P4\I
3G8>
+ 3.3VA
49.9 R48 0.1UF C4
10UF
C1
C69
C70
+
E
3.3VA
49.9 R49
E
0.1UF C66 220 330 R41 R40
C65
100NH L7 C77 0.01UF
220
R39
100NH L8 C78 0.01UF
330
R38
49.9
6
2
49.9
U3
13 14 15 16 11 12
R44
U4 TXD_N3\I RXD_P3\I RXD_N3\I SD3\I
13 14 15 16 11 12
VCCT VCCR GND GND GND GND TXDP TXDN HFCT5905 RXDP RXDN SD TDIS VEER
1
VCCT VCCR
3F8> 3F8< 3F8< 3F8<
9 10 5 4 3 8 R52 150 R56 150 150 R60
D
GND GND GND GND
TXDP TXDN HFCT5905 RXDP RXDN SD TDIS VEER
1
9 10 5 4 3 8 R53 150 R57 150 150 R61
R45
6
2
TXD_N4\I RXD_P4\I RXD_N4\I SD4\I
3G8> 3F8< 3F8< 3F8<
D
CHASS1 CHASS2 VEET
7
CHASS1 CHASS2 VEET
7
C
C
B
B
DRAWING: TITLE=OPTICS_BLOCK LAST_MODIFIED=Thu Jun 15 10:02:29 2000
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-991245 DOCUMENT ISSUE NUMBER: 1 TITLE: SPECTRA 4X155 REFERENCE DESIGN OPTICS_BLOCK ENGINEER: 10 9 8 7 6 5 4 3 MB 2 ISSUE DATE: 00/06/09 REVISION NUMBER: 1 PAGE:2 1 OF 16 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
2E2< 2D2< 2D2> 2D2> 2D2> 2E6< 2D6<
TXD_P4\I TXD_N4\I RXD_P4\I RXD_N4\I SD4\I TXD_P3\I TXD_N3\I RXD_P3\I RXD_N3\I SD3\I TXD_P2\I TXD_N2\I RXD_P2\I RXD_N2\I SD2\I TXD_P1\I TXD_N1\I RXD_P1\I RXD_N1\I SD1\I
50 OHM 50 OHM 50 OHM 50 OHM
158 158
R6 R5 100
0.1UF 0.1UF R4
C14 C13
AA2 AA3 AB3 AB2 AB1
50 OHM 50 OHM 50 OHM 50 OHM
158 158
R9 R8 100
0.1UF 0.1UF R7
C16 C15
W2 W3 Y1 Y2 Y3
F
2D6> 2D6> 2D6> 2H2< 2G2< 2F2> 2F2> 2F2>
SOIC U9 SPECTRA4-155 PM5316 1 OF 6 TXD4P CP4 CN4 TXD4N CP3 CN3 RXD4P RXD4N CP2 CN2 SD4 CP1 CN1 TXD3P TCLK TXD3N RCLK4 RCLK3 RXD3P RCLK2 RXD3N RCLK1 SD3 TXD2P TXD2N RXD2P RXD2N SD2 TXD1P TXD1N RXD1P RXD1N SD1 REFCLK PGMTCLK PGMRCLK ATP3 ATP2 ATP1 ATP0 PECLV
G J1
AD2 AD3 U3 U2 N3 N2 G2 G3 C6 E7 B6 D7 C7 V5 W1 V4 V3 D2 C87 0.22UF C79 0.22UF C85 0.22UF C86 0.22UF
1 2 3 4 5 6
1 3 5 7 9 11
GND TCLK RCLK4 RCLK3 RCLK2 RCLK1 J2
2 4 6 8 10 12
5
2
JMP POSTION
3
SMB
4 1
F
HEADER_6X2
50 OHM 50 OHM 50 OHM 50 OHM
158 158
R12 0.1UF R11 0.1UF 100 R10
C18 C17
L3 L2 M1 M2 M3
4.7K
E
2H6< 2G6< 2F6> 2F6> 2F6>
50 OHM 50 OHM 50 OHM 50 OHM
158 158
R15 0.1UF R14 0.1UF 100 R13
C20 C19
J3 J2 K2 K3 K4 B4
R62
E
E6 D6
PGMTCLK PGMRCLK
1 2
OVERHEAD<18..1>\I
6G2>
6G9>
13D4<
LINE SIDE
3.3 V D
TERMINATION RESISTORS AND CAPACITORS SHOULD BE PLACED NEAR U9
1 2
0.1UF
C109
HEADER2 J11 PLACE NEAR J15 REFCLK
D
Y1 3V3
4 8 5 56 R63 2
J4
1
JUMPER 1-2 2-3 EXT_REFCLK LOCALCLK
GND 19.44MHZ 20PPM
OUT
LOCALCLK
3
HEADER3
EXT_REFCLK
C
C
J3
2 5
3
SMB
4 1
SUPPLY A 19.44 MHZ EXTERNAL REFERENCE CLOCK B B
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-991245 DOCUMENT ISSUE NUMBER: 1 DRAWING: TITLE=SPECTRA_4X155_BLOCK LAST_MODIFIED=Thu Jun 15 10:02:32 2000 10 9 8 7 6 5 4 3 TITLE: SPECTRA 4X155 REFERENCE DESIGN SPECTRA_4X155_BLOCK ENGINEER: MB 2 ISSUE DATE: 00/06/09 REVISION NUMBER: 1 PAGE:3 1 OF 16 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
5 8
RN15 RN13
4 4.7K 1 4.7K
G RN8 RN30 RN9 RN8 RN9 RN30 RN30 RN9 RN29 RN11 RN11 RN11 RN11 RN29 RN12 RN12 RN13 RN14 RN14 RN28 RN14 RN14 RN28 RN15
3 2 4 4 1 3 4 3 3 4 1 3 2 4 1 2 4 2 1 3 4 3 4 3 6 7 5 5 8 6 5 6 6 5 8 6 7 5 8 7 5 7 8 6 5 6 5 6
F
4.7K
R22 4.7K
R21 4.7K
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
7 6 5 4 3 2 1 0
9E9>
ADD_DATA<7..0>\I
AD31 AC28 AC29 AC30 AC31 AB27 AB28 AB29 V27 V28 V29 V30 V31 U27 U28 U29 M29 M30 M31 L28 L29 L30 K27 K28 G29 G30 G31 F27 F28 F29 F30 E28
AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
U9 SPECTRA4-155 PM5316 2 OF 6 AC1J1V1_4/AFP4 AC1J1V1_3/AFP3 AC1J1V1_2/AFP2 AC1J1V1_1/AFP1 ADP4 ADP3 ADP2 ADP1 APL4 APL3 APL2 APL1 ACK TPAIS TPAISCK TPAISFP
G
AB30 U30 K29 E29 AD30 W31 M28 G28 AB31 U31 K30 E30 E31 D26 E26 B27
RN10 RN12 RN15 RN8 RN10 RN28 RN10 RN12 RN15
7 5 7 8 5 7 8 6 8
2 4.7K 4 4.7K 2 4.7K
AC1J1V1_AFP\I
1 4.7K 4 4.7K 2 4.7K
9F3>
ADP\I
1 4.7K 3 4.7K 1 4.7K
9G3>
APL\I ACK\I
9F3> 13D1>
F
ADD TELECOM BUS E
1 2 3 4 5 6
R20
J9 P_1 P_2 P_3 P_4 P_5 P_6
E
D
DROP_DATA<7..0>\I
9B9<
TP6 TP3 TP15 TP4 TP16 TP5 TP17 TP7 TP18 TP19 TP8 TP10 TP21 TP20 TP9 TP22 TP11 TP23 TP24 TP12 TP13 TP25 TP26 TP14
T T T T T T T T T T T T T T T T T T T T T T T T
C
7 6 5 4 3 2 1 0
AG31 AF29 AF30 AE27 AE28 AE29 AE30 AE31 AA29 AA30 Y27 Y28 Y29 Y30 Y31 W27 P27 P28 P29 P30 P31 N27 N28 N29 J27 J28 J29 J30 J31 H27 H28 H29 AF28 AA28 R28 K31
U9 SPECTRA4-155 PM5316 3 OF 6 DD31 DC1J1V1_4 DD30 DC1J1V1_3 DD29 DC1J1V1_2 DD28 DC1J1V1_1 DD27 DD26 DPL4 DD25 DPL3 DD24 DPL2 DD23 DPL1 DD22 DD21 DCK DD20 DFP DD19 DPAIS DD18 DPAISCK DD17 DPAISFP DD16 DD15 DD14 DD13 DD12 DD11 DD10 DD9 DD8 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 DDP4 DDP3 DDP2 DDP1 DROP TELECOM BUS
AD27 W28 N30 H30 AD28 W29 N31 H31 AH30 AG29 C27 D27 B28
RN30 RN29 RN13 RN9 RN10 RN13
8 7 7 7 6 6
1 4.7K 2 4.7K 2 4.7K
DC1J1V1\I
2 4.7K 3 4.7K 3 4.7K
9C3<
D DPL\I DCK\I RJ0FP_SPECTRA\I
9C3< 13D1>
4.7K
R25 4.7K
R24 4.7K
R23
C
RN8 RN29 RN28
9C3<
2 1 1
7 8 8
4.7K 4.7K 4.7K
DDP\I
B
B
DRAWING: TITLE=SPECTRA_4X155_BLOCK LAST_MODIFIED=Thu Jun 15 10:02:36 2000
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-991245 DOCUMENT ISSUE NUMBER: 1 TITLE: SPECTRA 4X155 REFERENCE DESIGN SPECTRA_4X155_BLOCK ENGINEER: 10 9 8 7 6 5 4 3 MB 2 ISSUE DATE: 00/06/09 REVISION NUMBER: 1 PAGE:4 1 OF 16 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
G
F
F
U9 LA<31..2>\I SPECTRA4-155 PM5316 4 OF 6
15 14 13 12 11 10 9 8 7 6 5 4 3 2 E18 C18 D18 B18 A18 E17 D17 C17 B17 A17 A15 C15 B15 D15 AK4 AK5 AH6 AG6 AJ5
14D4>
E
4 3
3.3 V
5
6
4.7K RN3
A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 TCK TDI TDO TMS TRSTB
D7 D6 D5 D4 D3 D2 D1 D0 INTB MBEB RDB/E RSTB WRB/RWB ALE CSB
4.7K
4.7K
D20 C20 B20 A20 E19 D19 C19 B19 A19 C14 B14 E14 D14 A14 E15
7 6 5 4 3 2 1 0
LD<31..0>\I 3.3 V
10F4<> 13G1>
14H4<> 13H10<
R66
R65
E INTB_SPECTRA\I RDB\I RESETB\I WRB\I CSB_SPECTRA\I
13E7< 13E1> 13B1> 13E1> 13E1>
RN3
4.7K
TP1 T
8
4.7K
RN3
MICRO D
3.3 V D RN3
2
C
7
1
C
B
B
DRAWING: TITLE=SPECTRA_4X155_BLOCK LAST_MODIFIED=Thu Jun 15 10:02:38 2000
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-991245 DOCUMENT ISSUE NUMBER: 1 TITLE: SPECTRA 4X155 REFERENCE DESIGN SPECTRA_4X155_BLOCK ENGINEER: 10 9 8 7 6 5 4 3 MB 2 ISSUE DATE: 00/06/09 REVISION NUMBER: 1 PAGE:5 1 OF 16 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
18 17 16 15 14 13 12 11
10 9 8 7 6 5 4 3
13D4< 6G2>
3E3>
OVERHEAD<18..1>\I
OVERHEAD<18..1>\I
3E3>
6G9>
13D4<
G SALM<4..1>\I
4 3 2 1
G
13D10<
U9
1 2 3 4 5 6 7 8 AK12 AK10 AL8 AJ7 AL12 AL10 AH9 AK7 AJ12 AJ10 AG9 AH7 AL18 AL17 AG15 AG14 AK18 AK17 AH15 AH14 A27 C26 E25 B26 D23 C21 B21 D13 C13 B13 A13 B10 C11 D12 A12 A10 B11 C12 E13 C10 D11 E12 B12 C22 B22 A22 D21 D24 C24
RTOHCLK4 RTOHCLK3 RTOHCLK2 RTOHCLK1 RTOH4 RTOH3 RTOH2 RTOH1 RTOHFP4 RTOHFP3 RTOHFP2 RTOHFP1 RSLDCLK4 RSLDCLK3 RSLDCLK2 RSLDCLK1 RSLD4 RSLD3 RSLD2 RSLD1 RPOHCLK RPOHFP RPOH RPOHEN RAD B3E RALM SALM4 SALM3 SALM2 SALM1
SPECTRA4-155 PM5316 5 OF 6
TTOHCLK4 TTOHCLK3 TTOHCLK2 TTOHCLK1 TTOH4 TTOH3 TTOH2 TTOH1 TTOHFP4 TTOHFP3 TTOHFP2 TTOHFP1 TTOHEN4 TTOHEN3 TTOHEN2 TTOHEN1 TSLDCLK4 TSLDCLK3 TSLDCLK2 TSLDCLK1 TSLD4 TSLD3 TSLD2 TSLD1 TPOHCLK TPOHFP TPOH TPOHEN TPOHRDY TAD TAFP TACK
AG13 AH11 AJ9 AG8 AK13 AG12 AL9 AJ8 AH13 AJ11 AK9 AL7 AJ13 AK11 AG10 AH8 AJ18 AJ17 AJ15 AJ14 AH18 AH17 AK15 AK14 D25 C25 A25 E24 B25 A24 B24 E23 C8 A8 B9 D10 D8 E9 C9 A9 A7 B8 D9 E10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 13 14 15 16 17 18 19 20 21 22 23 24
F
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 2 3 4 5 6 7 8 9 10 11 12
F
E
E
RECEIVE_OVERHEAD<32..1>
TRANSMIT_OVERHEAD<32..1>
LRDI4/RRCPCLK4 LRDI3/RRCPCLK3 LRDI2/RRCPCLK2 LRDI1/RRCPCLK1 LOS4/RRCPFP4 LOS3/RRCPFP3 LOS2/RRCPFP2 LOS1/RRCPFP1 LAIS4/RRCPDAT4 LAIS3/RRCPDAT3 LAIS2/RRCPDAT2 LAIS1/RRCPDAT1 LOF4 LOF3 LOF2 LOF1
RLAIS4/TRCPCLK4 RLAIS3/TRCPCLK3 RLAIS2/TRCPCLK2 RLAIS1/TRCPCLK1 TLRDI4/TRCPFP4 TLRDI3/TRCPFP3 TLRDI2/TRCPFP2 TLRDI1/TRCPFP1 TLAIS4/TRCPDAT4 TLAIS3/TRCPDAT3 TLAIS2/TRCPDAT2 TLAIS1/TRCPDAT1
D
RING_CONTROL<24..1> P_1 P_2 P_3 P_4 P_5 P_6
D
4.7K 4.7K 4.7K 4.7K
4.7K 4.7K 4.7K 4.7K
4.7K 4.7K 4.7K 4.7K
4.7K 4.7K 4.7K 4.7K
J8 PLACE NEAR J15
C
RN27 RN27 RN27 RN27
RN4 RN4 RN4 RN4
RN5 RN5 RN5 RN5
RN6 RN6 RN6 RN6
RN7 RN7 RN7 RN7
R68
1 2 3 4
1 2 3 4
1 2 3 4
1 2 4 3
4 3 2 1
4.7K
RTCEN RTCOH
RX/TX OVERHEAD
4.7K 4.7K 4.7K 4.7K
1 2 3 4 5 6
RING_CONTROL<24..1>
8 7 6 5
8 7 6 5
8 7 6 5
8 7 5 6
5 6 7 8
C
J14
MICTOR 38 PIN 1 2 3 4 5 6 7 8 9 10 11 12 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37
P1 P3 P5 P7 P9 P11 P13 P15 P17 P19 P21 P23 P25 P27 P29 P31 P33 P35 P37 P2 P4 P6 P8 P10 P12 P14 P16 P18 P20 P22 P24 P26 P28 P30 P32 P34 P36 P38
B RING_CONTROL<24..1>
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38
13 14 15 16 17 18 19 20 21 22 23 24
50 MIL J15 RECEIVE_OVERHEAD<32..1>
A<32..1> B<32..1>
TRANSMIT_OVERHEAD<32..1> B
HEADER 32X2
RING_CONTROL<24..1>
39 40 41 42 43
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-991245 DOCUMENT ISSUE NUMBER: 1 DRAWING: TITLE=SPECTRA_4X155_BLOCK TITLE: SPECTRA 4X155 REFERENCE DESIGN SPECTRA_4X155_BLOCK ISSUE DATE: 00/06/09 REVISION NUMBER: 1 PAGE:6 2 1 OF 16 A
A
LAST_MODIFIED=Thu Jun 15 10:02:41 2000MB ENGINEER: 10 9 8 7 6 5 4 3
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G 3.3 V
A2 A3 A4 A6 A11 A16 A21 A26 A28 A29 A30 B1 B3 B16 B29 B31 C1 C2 C30 C31 D1 D31 F1 F31 L1 L31 T1 T2 T30 T31 AA1 AA31 AF1 AF31 AH1 AH31 AJ1 AJ2 AJ30 AJ31 AK1 AK3 AK16 AK29 AK31 AL2 AL3 AL4 AL6 AL11 AL16 AL21 AL26 AL28 AL29 AL30 AE1 F2 R3 R1 K1 H5 H4
G U9 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND QAVS1 QAVS0 TAVS1_A TAVS1_B RAVS1_A RAVS1_B RAVS1_C RAVS2_A RAVS2_B RAVS2_C RAVS3_A RAVS3_B RAVS3_C RAVS4_A RAVS4_B RAVS4_C
0.1UF 0.1UF 0.1UF 0.1UF
SPECTRA4-155 PM5316 6 OF 6
3.3 V VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
A1 A31 B2 B30 C3 C4 C16 C28 C29 D3 D4 D16 D28 D29 E5 E11 E16 E21 E27 L5 L27 T3 T4 T5 T27 T28 T29 AA5 AA27 AG5 AG11 AG16 AG21 AG27 AH3 AH4 AH16 AH28 AH29 AJ3 AJ4 AJ16 AJ28 AJ29 AK2 AK30 AL1 AL31 E20 AK28 G5 AD5 R4 R2 L4 G4 H3 M4 N1 P4 Y4 U1 V1 AB5 AD4 AC3 9 8 7 6 5 4 3 2 1 0 0 47UF 47UF 0.1UF 27 R16
0.1UF
C90 0.1UF
C95 0.1UF
C118 0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C100 0.1UF
3.3VA AVD<9..0>
9 47UF 27 R3 47UF 47UF R19 0.1UF C94
C119
C115
C102
C103
C88
C89
3.3VA
6 0.1UF
27
PLACE 0.1UF CAPACITOR AS CLOSE TO POWER PIN AS POSSIBLE F
+
+
C80
C28
C27
F 3.3 V
0.1UF
C108 0.1UF
C105 0.1UF
C92 0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C114 0.1UF
C112
C107
C104
C116
C113
3.3VA
0.1UF 47UF 47UF R18
C12
+
C10
C97
0.1UF
C106
0.1UF
R67
C81
C26
E
PLACE DECOUPLING CAPS CLOSE TO THE FOLLOWING PINS: B30 B2 D28 D16 D4 E21 E11 L27 L5 T28 T4 AA27 AA5 AG21 AG11 AH28 AH16 AH4 AK30 AK2
3.3VA
2 47UF 47UF 0.1UF 27 R17 7 5 3 1 0.1UF 47UF 27 R2
C25
C82
+
+
+ 47UF
1.0K
4
27
8
2.7 R1
E
+
C83 C23
+
100 R64 0.1UF C101
C24
C99
VBIAS0 VBIAS1 QAVD0 QAVD1 TAVD1_A TAVD1_B RAVD1_A RAVD1_B RAVD1_C RAVD2_A RAVD2_B RAVD2_C RAVD3_A RAVD3_B RAVD3_C RAVD4_A RAVD4_B RAVD4_C
D
C11
+
D
+
C21
C84
3.3 V
C30 10UF C46 10UF C38 10UF C32 10UF C31 10UF C29 10UF C33 10UF C47 10UF
M5 N4 P5 Y5 U4 V2 AB4 AC5 AC4
+
+
+
+
+
+
+
C
+
C22
+
C 3.3VA POWER
PLACE CAPS CLOSE TO EACH OF THE RAVD_A PINS
C96
C91
C93
C98
PLACE 2 PER EDGE AROUND SPECTRA 4X155
B
5V
B 3.3V U7 LM1085 INPUT OUTPUT
TAB ADJ/GND
3.3VA
2 1 10UF
3 4 10UF
3.3V_REGULATED DRAWING: TITLE=SPECTRA_4X155_BLOCK +
C9
+
C8
LAST_MODIFIED=Thu Jun 15 10:02:46 2000
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-991245 DOCUMENT ISSUE NUMBER: 1 TITLE: SPECTRA 4X155 REFERENCE DESIGN SPECTRA_4X155_BLOCK ENGINEER: 10 9 8 7 6 5 4 3 MB 2 ISSUE DATE: 00/06/09 REVISION NUMBER: 1 PAGE:7 1 OF 16 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
G
UBGA U15 TWRK<8..1>\I TBS PM5310 1 of 5 RPWRK[4] TPWRK[4] RNWRK[4] TNWRK[4] TPWRK[3] TNWRK[3] TPWRK[2] TNWRK[2] TPWRK[1] TNWRK[1] RPWRK[3] RNWRK[3] RPWRK[2] RNWRK[2] RPWRK[1] RNWRK[1] RWRK<8..1>\I
12F10<
8 7 6 5 4 3 2 1
TPWRK4 TNWRK4 TPWRK3 TNWRK3 TPWRK2 TNWRK2 TPWRK1 TNWRK1 TPPROT4 TNPROT4 TPPROT3 TNPROT3 TPPROT2 TNPROT2 TPPROT1 TNPROT1 TPAUX4 TNAUX4 TPAUX3 TNAUX3 TPAUX2 TNAUX2 TPAUX1 TNAUX1 TJ0FP\I TCMP\I
50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM
K24 K23 K26 K25 J25 J24 H24 H23 T25 T24 R26 R25 R24 R23 P26 P25 AA26 AA25 AA24 AA23 Y25 Y24 W26 W25 AC22 C23 AB25 AB23
H25 H26 G24 G25 F23 F24 F25 F26 N25 N26 M23 M24 M25 M26 L24 L25 W23 W24 V24 V25 U25 U26 U23 U24 AD23 A24 AD12 C22
50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM
RPWRK4 RNWRK4 RPWRK3 RNWRK3 RPWRK2 RNWRK2 RPWRK1 RNWRK1 RPPROT4 RNPROT4 RPPROT3 RNPROT3 RPPROT2 RNPROT2 RPPROT1 RNPROT1 RPAUX4 RNAUX4 RPAUX3 RNAUX3 RPAUX2 RNAUX2 RPAUX1 RNAUX1 RJ0FP_TBS\I OCMP\I SYSCLK\I RWSEL\I
8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1
12F10>
F
F
12G10<
TPROT<8..1>\I
8 7 6 5 4 3
TPPROT[4] RPPROT[4] TNPROT[4] RNPROT[4] TPPROT[3] RPPROT[3] TNPROT[3] RNPROT[3] TPPROT[2] RPPROT[2] TNPROT[2] RNPROT[2] TPPROT[1] RPPROT[1] TNPROT[1] RNPROT[1] TPAUX[4] TNAUX[4] TPAUX[3] TNAUX[3] TPAUX[2] TNAUX[2] TPAUX[1] TNAUX[1] TJ0FP TCMP RPAUX[4] RNAUX[4] RPAUX[3] RNAUX[3] RPAUX[2] RNAUX[2] RPAUX[1] RNAUX[1] RJ0FP OCMP SYSCLK RWSEL
RPROT<8..1>\I
12G10>
E
12C10<
2 1
E RAUX<8..1>\I
12A10>
TAUX<8..1>\I
8 7 6 5 4 3 2 1
13D8< 13D8>
D
ATB1 ATB0 SERIAL TELECOMBUS
13D8> 13D8> 13D1> 13D8>
D
C
C
B
B
DRAWING: TITLE=TBS_BLOCK LAST_MODIFIED=Thu Jun 15 10:02:48 2000
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-991245 DOCUMENT ISSUE NUMBER: 1 TITLE: SPECTRA 4X155 REFERENCE DESIGN TBS_BLOCK ENGINEER: 10 9 8 7 6 5 4 3 MB 2 ISSUE DATE: 00/06/09 REVISION NUMBER: 1 PAGE:8 1 OF 16 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
UBGA U15 TBS PM5310 2 of 5 OD[4][7] ODP[4] OD[4][6] ODP[3] OD[4][5] ODP[2] OD[4][4] ODP[1] OD[4][3] OD[4][2] OPL[4] OD[4][1] OPL[3] OD[4][0] OPL[2] OPL[1] OD[3][7] OD[3][6] OJ0J1[4] OD[3][5] OJ0J1[3] OD[3][4] OJ0J1[2] OD[3][3] OJ0J1[1] OD[3][2] OD[3][1] OPAIS[4] OD[3][0] OPAIS[3] OPAIS[2] OD[2][7] OPAIS[1] OD[2][6] OD[2][5] OTV5[4] OD[2][4] OTV5[3] OD[2][3] OTV5[2] OD[2][2] OTV5[1] OD[2][1] OD[2][0] OTPL[4] OTPL[3] OD[1][7] OTPL[2] OD[1][6] OTPL[1] OD[1][5] OD[1][4] OTAIS[4] OD[1][3] OTAIS[3] OD[1][2] OTAIS[2] OD[1][1] OTAIS[1] OD[1][0] OCOUT[4] OCOUT[3] OCOUT[2] OCOUT[1]
OUTGOING TELECOMBUS
G
TP61 TP60 TP71 TP70 TP69 TP59 TP67 TP68 TP43 TP53 TP52 TP48 TP51 TP50 TP49 TP40 TP37 TP33 TP41 TP30 TP32 TP28 TP29 TP36
7 6 5 4 3 2 1 0
T T T T T T T T T T T T T T T T T T T T T T T T
AF16 AD15 AE15 AF15 AD14 AE13 AD13 AF12 AA4 AC1 AB2 Y4 AB1 AA2 Y3 W4 M3 L1 M4 L2 K1 L3 K2 L4 D6 A4 B5 C6 D7 A5 C7 A6
AF17 AB4 M1 A3 AC12 Y2 J1 B7 AE11 W3 K3 C8 AD16 AD4 N3 D3 AD17 AD5 P3 D2 AF18 AE4 P2 C1 AE17 AC5 N2 E4 AC15 AD1 M2 B4
T TP74 T TP47 T TP34 T TP57 T TP44 T TP31 T TP58 T TP46 T TP27 T TP72 T TP55 T TP45 T TP63 T TP56 T TP42 T TP64 T TP65 T TP39 T TP73 T TP66 T TP38 T TP62 T TP54 T TP35
ADP\I
4F2<
APL\I
4F2<
AC1J1V1_AFP\I
4G2<
F
F
4E10<
ADD_DATA<7..0>\I
1 2 3 4 5
J12 P_1 P_2 P_3 P_4 P_5
HEADER5
E
E
8
4.7K1 RN20 4.7K4 RN19 4.7K1 RN23 D
D UBGA U15 TBS PM5310 3 of 5 PLACE RESISTORS CLOSE TO RN24 1 8 RN33 3 6 RN24 4 5 RN24 3 6 RN24 2 7 RN23 3 6 RN33 2 7 RN23 4 5 C RN34 RN34 RN21 RN21 RN21 RN34 RN20 RN20 RN18 RN18 RN18 RN32 RN17 RN32 RN17 RN32
2 3 3 4 1 1 4 3 1 3 2 3 4 1 3 2 7 6 6 5 8 8 5 6 8 6 7 6 5 8 6 7
5 8
PINS 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
7 6 5 4 3 2 1 0
AD21 AC20 AF22 AE21 AF21 AE20 AD19 AF20 AC10 AD9 AF7 AD8 AF6 AC8 AE6 AF5 U3 V1 U2 T3 T2 R4 T1 R3 G2 F1 G3 F2 E1 G4 F3 E2
ID[4][7] ID[4][6] ID[4][5] ID[4][4] ID[4][3] ID[4][2] ID[4][1] ID[4][0] ID[3][7] ID[3][6] ID[3][5] ID[3][4] ID[3][3] ID[3][2] ID[3][1] ID[3][0]
IDP[4] IDP[3] IDP[2] IDP[1] IPL[4] IPL[3] IPL[2] IPL[1] IJOJ1[4] IJOJ1[3] IJOJ1[2] IJOJ1[1]
AE22 AE9 V2 G1 AD18 AD6 R2 F4 AF19 AF4 R1 E3 AF23 AD10 W1 H2 AF24 AD11 W2 H1 AE23 AE10 V3 K4 AC21 AF9 U4 J3
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
8 8 5 8 7 7 7 7 8 7 5 7 5 5 6 6 6 8 5 7 5
1 1 4 1 2 2 2 2 1 2 4 2 4 4 3 3 3 1 4 2 4
RN25 RN22 RN18 DDP\I RN33 RN21 RN17 DPL\I RN23 RN20 RN17 DC1J1V1\I RN25 RN34 RN19 RN25 RN22 RN19 RN25 RN22 RN19 RN33 RN22 RN32 4.7K 4.7K 4.7K 4.7K
1 2 3 4
4C10>
4D2>
C
4D2>
B
4C10>
DROP_DATA<7..0>\I
IPAIS[4] IPAIS[3] IPAIS[2] ID[2][7] IPAIS[1] ID[2][6] ITV5[4] ID[2][5] ITV5[3] ID[2][4] ITV5[2] ID[2][3] ITV5[1] ID[2][2] ID[2][1] ITPL[4] ID[2][0] ITPL[3] ITPL[2] ID[1][7] ITPL[1] ID[1][6] ID[1][5] ID[1][4] ITAIS[4] ID[1][3] ITAIS[3] ID[1][2] ITAIS[2] ID[1][1] ITAIS[1] ID[1][0]
INCOMING TELECOMBUS
J13 P_1 P_2 P_3 P_4 HEADER4 B
5
6
7
8
DRAWING: TITLE=TBS_BLOCK
4 3 2 1
LAST_MODIFIED=Thu Jun 15 10:02:52 2000
RN16 RN16 RN16 RN16
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-991245 DOCUMENT ISSUE NUMBER: 1 TITLE: SPECTRA 4X155 REFERENCE DESIGN TBS_BLOCK ENGINEER: 10 9 8 7 6 5 4 3 MB 2 ISSUE DATE: 00/06/09 REVISION NUMBER: 1 PAGE:9 1 OF 16 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
G
F UBGA U15 LA<31..2>\I TBS PM5310 4 of 5 A[11]/TRS D[15] D[14] A[10] A[9] D[13] A[8] D[12] A[7] D[11] A[6] D[10] A[5] D[9] A[4] D[8] A[3] D[7] A[2] D[6] A[1] D[5] A[0] D[4] D[3] D[2] D[1] D[0] RSTB CSB WRB RDB ALE INTB TRSTB TCK TMS TDI TDO LD<31..0>\I
F
14D4>
E
3
3.3 V RN31 4.7K
1
4.7K RN31
2
13 12 11 10 9 8 7 6 5 4 3 2
B13 B14 A15 B15 C15 A16 D15 B16 A17 C16 B17 D16
6
8
RN31
13B1> 13E1> 13E1> 13E1> 13E7<
RESETB\I CSB_TBS\I WRB\I RDB\I INTB_TBS\I
RN315
A23 D17 B19 B18 C17 A20
B21 C21 D20 D19 B20
T TP2 4.7K
MICRO JTAG
7
D
4
4.7K
A7 B8 C9 D10 B9 C10 A9 D11 B10 C11 B11 D12 A11 C12 B12 A12
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
5E4<>
13G1>
14H4<> 13H10<
3.3 V E
D
C
C
B
B
DRAWING: TITLE=TBS_BLOCK LAST_MODIFIED=Thu Jun 15 10:02:55 2000
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-991245 DOCUMENT ISSUE NUMBER: 1 TITLE: SPECTRA 4X155 REFERENCE DESIGN TBS_BLOCK ENGINEER: 10 9 8 7 6 5 4 3 MB 2 ISSUE DATE: 00/06/09 REVISION NUMBER: 1 PAGE:10 1 OF 16 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
G
3.3VA
3.3 V UBGA U15 3.3 V TBS PM5310 5 of 5 VDDO0 VSS39 VDDO1 VSS38 VDDO2 VSS37 VDDO3 VSS36 VDDO4 VSS35 VDDO5 VSS34 VDDO6 VSS33 VDDO7 VSS32 VDDO8 VSS31 VDDO9 VSS30 VDDO10 VSS29 VDDO11 VSS28 VDDO12 VSS27 VDDO13 VSS26 VDDO14 VSS25 VDDO15 VSS24 VDDO16 VSS23 VDDO17 VSS22 VDDO18 VSS21 VDDO19 VSS20 VDDO20 VSS19 VSS18 VDDI19 VSS17 VDDI18 VSS16 VDDI17 VSS15 VDDI16 VSS14 VDDI15 VSS13 VDDI14 VSS12 VDDI13 VSS11 VDDI12 VSS10 VDDI11 VSS9 VDDI10 VSS8 VDDI9 VSS7 VDDI8 VSS6 VDDI7 VSS5 VDDI6 VSS4 VDDI5 VSS3 VDDI4 VSS2 VDDI3 VSS1 VSS0 VDDI2 VDDI1 VDDI0 RES CSU_AVDH AVDH6 AVDH5 AVDH4 AVDH3 AVDH2 AVDH1 AVDH0 AVDL5 AVDL4 AVDL3 AVDL2 AVDL1 AVDL0 POWER RESK
0.1UF
C134 0.1UF
C166 0.1UF
C123 0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C143 0.1UF
C160 0.1UF
0.1UF
C163 0.1UF
C162 0.1UF
C145
C154
C165
C158
C177
C149
C168
F 3.3 V
1.8 V
V4 N4 H4 D8 D4 D23 D18 D13 C3 C24 B25 B2 AE25 AE2 AD3 AD24 AC9 AC4 AC23 AC19 AC14 A18 A21 A8 AC2 AD20 AD22 AD7 AE12 AE18 AE5 AE8 B6 C13 D1 D21 H3 J2 P4 U1 Y1 N23
E
1.8 V
0.1UF
C127 0.1UF
C139 0.1UF
C172 0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C151 0.1UF
0.1UF
0.1UF
C159 0.1UF
3.3VA
C126 2.7 R33
A1 A13 A14 A2 A25 A26 AB26 AC25 AC26 AD2 AD25 AD26 AE1 AE24 AE26 AE3 AF1 AF13 AF14 AF2 AF25 AF26 B1 B24 B26 B3 C2 C25 C26 D25 D26 E26 G26 J26 L26 N1 P1 T26 V26 Y26 E25 3.16K E23 R69
F
0.1UF
C164 0.1UF
C140 0.1UF
C138 0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C157 0.1UF
C161 0.1UF
0.1UF
C122 0.1UF
C170 0.1UF
C130
C135
C169
C131
C137
C124
C125
3.3 V ADJ U12 LM1085 INPUT OUTPUT
TAB ADJ/GND
1.8 VA
3 4 10UF C48
2 1 44.2 100 R29 10UF C53 10UF
E +
C54
+
C155
C128
C136
C141
C173
C167
C129
3.3VA
0.1UF C148 47UF C56
+
D 1.8 VA 1.8 VA 1.8 V
AB24 AC24 D24 E24 J23 T23 Y23 G23 L23 P23 N24 P24 V23
R30
+
D
0.1UF
C147 0.1UF
C150 0.1UF
C152 0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C133 0.1UF
0.1UF
C153
C156
C142
C174
C175
C176
C171
0.1UF
C
C144
C
PLACE DECOUPLING CAPS CLOSE TO EACH POWER PIN 3.3 V 1.8 V
10UF
C61 10UF
C55 10UF
C59 10UF
10UF
C49 10UF
C60 10UF
C62 10UF
C58 10UF
C41 10UF
C57 10UF
C42 10UF
+
+
+
+
+
+
+
+
+
+
+
C43
C52
+
B
B
DRAWING: TITLE=TBS_BLOCK PLACE 3 PER EDGE AROUND TBS LAST_MODIFIED=Thu Jun 15 10:02:58 2000
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-991245 DOCUMENT ISSUE NUMBER: 1 TITLE: SPECTRA 4X155 REFERENCE DESIGN TBS_BLOCK ENGINEER: 10 9 8 7 6 5 4 3 MB 2 ISSUE DATE: 00/06/09 REVISION NUMBER: 1 PAGE:11 1 OF 16 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
WORKING AND PROTECT LVDS LINKS
8F8> 8F3<
FEMALE_RA J6
AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10
TPROT<8..1>\I RPROT<8..1>\I
8 6 4 2 1 3 5 7 8 6 4 2 1 3 5 7
G FEMALE_RA J6
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AMP_HS3_6X10
G
FEMALE_RA J6
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10
FEMALE_RA J6
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 AMP_HS3_6X10
RPPROT4 RPPROT3 RPPROT2 RPPROT1 RPWRK4 RPWRK3 RPWRK2 RPWRK1
50 50 50 50 50 50 50 50
OHM OHM OHM OHM OHM OHM OHM OHM
50 50 50 50 50 50 50 50
OHM OHM OHM OHM OHM OHM OHM OHM
RNPROT4 RNPROT3 RNPROT2 RNPROT1 RNWRK4 RNWRK3 RNWRK2 RNWRK1
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
C1 D1 C2 D2 C3 D3 C4 D4 C5 D5 C6 D6 C7 D7 C8 D8 C9 D9 C10 D10 AMP_HS3_6X10
TPPROT4 TPPROT3 TPPROT2 TPPROT1 TPWRK4 TPWRK3 TPWRK2 TPWRK1
50 50 50 50 50 50 50 50
OHM OHM OHM OHM OHM OHM OHM OHM
50 50 50 50 50 50 50 50
OHM OHM OHM OHM OHM OHM OHM OHM
TNPROT4 TNPROT3 TNPROT2 TNPROT1 TNWRK4 TNWRK3 TNWRK2 TNWRK1
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10
E1 F1 E2 F2 E3 F3 E4 F4 E5 F5 E6 F6 E7 F7 E8 F8 E9 F9 E10 F10 AMP_HS3_6X10
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10
FEMALE_RA J6
CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10
CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 AMP_HS3_6X10
F FEMALE_RA J6
8F3< 8F8>
F
RWRK<8..1>\I
8 6 4 2 1 3 5 7
TWRK<8..1>\I
13D8> 13F10<
TJ0FP_OUT\I SYSCLK1P\I SYSCLK1N\I RJ0FP_IN\I RWSEL_IN\I SYSCLK2P\I SYSCLK2N\I XCMP_IN\I 50 OHM 50 OHM 50 OHM 50 OHM
EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10
EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10 AMP_HS3_6X10
8 6 4 2
1 3 5 7
E
13F10< 13D8< 13D8< 13F10< 13F10< 13D8<
E
D
TPROT<8..1>, TWRK<8..1>, RWRK<8..1>, RPROT<8..1>, TAUX<8..1> AND RAUX<8..1> CONSIST OF DIFFERENTIAL LVDS PAIRS. EACH PAIR SHOULD BE ROUTED TOGETHER ON THE SAME LAYER AND HAVE THE SAME LENGTH. ALL LVDS TRACES SHOULD BE 50 OHM.
D
FEMALE_RA J5 AUXILLARY LVDS LINKS DO NOT POPULATE CONNECTOR IF AUXILLARY LVDS LINKS NOT REQUIRED C
8E8>
AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10
TAUX<8..1>\I
7 5 3 1 2 4 6 8
AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AMP_HS3_6X10
C
FEMALE_RA J5
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
FEMALE_RA J5
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
FEMALE_RA J5
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
FEMALE_RA J5
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10
B
A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 AMP_HS3_6X10
D1 C1 D2 C2 D3 C3 D4 C4 D5 C5 D6 C6 C7 D7 C8 D8 D9 C9 C10 D10 AMP_HS3_6X10
TNAUX4 TNAUX3 TNAUX2 TNAUX1 RNAUX4 RNAUX3 RNAUX2 RNAUX1
50 50 50 50
OHM OHM OHM OHM
50 50 50 50
OHM OHM OHM OHM
TPAUX4 TPAUX3 TPAUX2 TPAUX1 RPAUX4 RPAUX3 RPAUX2 RPAUX1
50 OHM 50 OHM 50 OHM 50 OHM
50 OHM 50 OHM 50 OHM 50 OHM
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10
E1 F1 E2 F2 E3 F3 E4 F4 E5 F5 E6 F6 E7 F7 E8 F8 E9 F9 E10 F10 AMP_HS3_6X10
CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 AMP_HS3_6X10
B
FEMALE_RA J5
EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10
DRAWING: TITLE=SYS_INTERFACE_BLOCK LAST_MODIFIED=Thu Jun 15 10:02:22 2000
8E3<
RAUX<8..1>\I
A
EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10 AMP_HS3_6X10
7 5 3 1
2 4 6 8
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-991245 DOCUMENT ISSUE NUMBER: 1 TITLE: SPECTRA 4X155 REFERENCE DESIGN SYSTEM_INTERFACE_BLOCK ENGINEER: MB 2 ISSUE DATE: 00/06/09 REVISION NUMBER: 1 PAGE:12 1 OF 16 A
10
9
8
7
6
5
4
3
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE
3.3 V LID D2
5 6 7 8 K1 K2 K3 K4 A1 A2 A3 A4
REV
DESCRIPTION
DATE
APPR
1
H LED_1 LED_2 LED_3
14H4<> 13G1> 10F4<> 5E4<> 14D4>
2 4 6 8
U8
A1 A2 A3 A4
H
OEA* YA1 YA2 YA3 YA4
18 4 16 3 14 2 12 1
RN2 RN2 RN2 RN2
68 68 68 68
3.3 V
LED SSF-LXH5147
0.1UF
LD<31..0>\I LA<31..2>\I
LED_4
PLACE NEAR LED DRIVER
C3
MC74AHC244ADW
LED_5 LED_6 LED_7
11 13 15 17
B1 B2 B3 B4 OEB*
19
YA1 YB2 YB3 YB4
9 7 5 3
4 3 2 1
RN1 RN1 RN1 RN1
68 68 68 68
LYD D1
5 6 7 8 K1 K2 K3 K4 A1 A2 A3 A4
LED SSF-LXH5147
G
LED_8
FOR DEBUGGING LD<31..0>\I J7 P_1 P_2 P_3 P_4 P_5 LA<31..2>\I
1 2 3 4 5 2 1 0 17 16
G
5E4<> 10F4<> 14H4<> 13H10< 14D4>
EXTERNAL SYSCLK
100 R31 1 2 100 R32 3 4 8
U13
LVPECL TTL
12E10> 12E10>
50 OHM SYSCLK1P\I 50 OHM SYSCLK1N\I 50 OHM SYSCLK2P\I 50 OHM SYSCLK2N\I 3.3 V
D0P D0N D1P D1N VCC
Q0 Q1 GND
7 6 5
56 R28 56 R27
SYSCLK1 SYSCLK2 3.3 V
MC100LVELT23
F
12E10> 12E10>
F
0.1UF
C44 0.1UF
C110 0.1UF
C39 0.1UF
C120 0.1UF
C121 0.1UF
C117 0.1UF
5 57 98
26 38 51 88
C111 10UF
C37 10UF
C45 10UF
C40 10UF
+
+
+
0.1UF
U11
C51
3.3 V
2 1 0 0.1UF C146 17 16 16 13 18 20 14 15 25 17 28 33 36 29 39 30 40 22 23 27 87 94 91 93 95 96 97 1 6 8 9 11 10 12 92 3 4 99
VCCINT VCCINT VCCINT
VCCIO VCCIO VCCIO VCCIO
C34
+
E
LOCAL SYSCLK Y2
1 4
14F2> 14F2> 14E2> 5E4> 10D9>
TRI GND 77.76MHZ 100PPM
3V3 OUT
8 5 56 R26
0.1UF
C35 0.1UF
14F2> 14E2<
L_WRB\I L_ADSB\I L_USERO\I INTB_SPECTRA\I INTB_TBS\I SYSCLK1 SYSCLK2 LOCAL_OSC L_WRB\I L_CLK\I
VCCA
6G9>
4 3 2 1
SALM<4>\I SALM<3>\I SALM<2>\I SALM<1>\I
D
12E10> 12E10< 12E10> 12D10> 8D4< 8D7> 8D4< 8D7< 8D4<
RJ0FP_IN\I TJ0FP_OUT\I RWSEL_IN\I XCMP_IN\I RJ0FP_TBS\I TJ0FP\I RWSEL\I TCMP\I OCMP\I
14F2> 14F2< 14F2< 16D8>
LHOLD\I LHOLDA\I L_READYB\I PWROK_1_8V\I
41 32 49 50 35 53 54 37 42 60 52 61 63 55 56 64 58 59 48 45 83 47
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
VCCB
SALM<4..1>\I
IO1 IO4 IO1 IO4 IO1 IO4 IO1 IO4 IO1 IO4 IO1 IO4 IO1 IO4 IO1 IO4 IO1 IO4 IO4 IO1 IO4 IO1 IO4 IO1 IO4 IO1 IO4 IO1 IO1 IO4 IO1/GCK1 IO4 IO1/GCK2 IO4 IO1/GCK3 IO4 XC9572XL IO2 TQ100 IO3 IO2 10NS IO3 IO3 IO2 IO3 IO2 IO3 IO2 IO3 IO2 IO3 IO2 IO3 IO2 IO3 IO2 IO3 IO2 IO3 IO2 IO2 IO3 IO2 IO3 IO2 IO3 IO2 IO3 IO2/GTS1 IO3 IO2/GTS2 IO3 IO3 IO2/GSR TCK TDI TDO TMS
65 67 71 72 68 76 77 70 66 81 74 82 85 78 89 86 90 79
RDB\I WRB\I CSB_SPECTRA\I CSB_TBS\I L_USERI\I L_INTB\I LED_1 LED_2 LED_3 LED_4 LED_5 LED_6 LED_7 LED_8 RJOFP_SPECTRA\I OVERHEAD<18..1>\I
3E3> 6G2> 6G9>
5E4< 10E9< 5E4< 10E9< 5E4< 10E9< 14E2< 14E2<
E 3.3 V
C36
U10
1
20
3.3 V
9 10
OEA INA
OA4 OA3 OA2 OA1 OA0 OB4 OB3 OB2 OB1 OB0
7 6 4 3 2 14 15 17 18 19 13
RN26 RN26 RN26
6 7 8
3 2 1
56 56 56
SYSCLK\I ACK\I DCK\I
8D4< 4F2< 4D2<
D
PI49FCT3805
12 11
OEB INB GNDA GNDB GNDQ
5 16 8
MON
3.3 V J10
2 4 6 8
TCK TDI TDO TMS
1 3 5 7
14E2>
GND GND GND GND GND GND GND GND
L_RSTOB\I
P_1 P_2 P_3 P_4 P_5 P_6 P_7 P_8
HEADER 4X2
3.3 V
0.1UF C6
SW1
2
PBNO
U5
4
U6
1 2 2
74HC08
VCC
MAX811T
1 3
21 31 44 62 69 75 84 100
C
PLACE 49FCT3805 CLOSE TO CPLD OUTPUT PIN
C
3
RESETB\I
5E4< 10E9<
MR
RESET GND
1
B
U6
4 5
74HC08
B
6
3.3 V U6
9 C7 10 0.1UF
74HC08
DRAWING: TITLE=CPLD_BLOCK LAST_MODIFIED=Thu Jun 15 10:02:25 2000
8
PLACE NEAR 74HC08
U6
12 13
74HC08
PMC-Sierra, Inc.
11
A
DOCUMENT NUMBER: PMC-991245 DOCUMENT ISSUE NUMBER: 1 TITLE: SPECTRA 4X155 REFERENCE DESIGN CPLD_BLOCK ENGINEER: 10 9 8 7 6 5 4 3 MB 2
ISSUE DATE: 00/06/09 REVISION NUMBER: 1 PAGE:13 1 OF 16
A
10
9
8
7
6
5
4
3
2
1
REVISIONS
CPCI BRIDGE
3.3 V H 3.3 V
4.7K R7_1
ZONE
REV
DESCRIPTION
DATE
APPR
H 3.3 V 3.3 V 3.3 V 3.3 V LD<31..0>\I
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
5E4<> 13G1>
10F4<> 13H10<
4.7K 4.7K 4.7K 4.7K
4.7K 4.7K 4.7K 4.7K
4.7K 4.7K 4.7K 4.7K
4.7K 4.7K 4.7K 4.7K
6 8 7 7
95 96 97 98 100 101 102 103 104 105 106 107 110 111 112 113 114 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131
15H8<>
AD<31..0>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 2 1 0
3.3 V
162 147 141 133 116 109 99 89 70 62 45 35 28 20 1 139 138 137 136 134 163 144 143 148 90 149 135 146 145 91 92 153 151 150 160 142 53 154 152 159 158 157 156 155 176 161 140 132 115 108 88 69 61 44 27 19
LD<31> LD<30> LD<29> LD<28> LD<27> LD<26> LD<25> LD<24> LD<23> LD<22> LD<21> LD<20> LD<19> LD<18> LD<17> LD<16> LD<15> LD<14> LD<13> LD<12> LD<11> LD<10> LD<9> LD<8> LD<7> LD<6> LD<5> LD<4> LD<3> LD<2> LD<1> LD<0>
7 6 5 8
6 8 6 7
7 5 8 5
G
F
15H8<>
C/BE<3..0>
AD<31> AD<30> AD<29> AD<28> AD<27> AD<26> AD<25> AD<24> AD<23> AD<22> AD<21> AD<20> AD<19> AD<18> AD<17> AD<16> AD<15> AD<14> AD<13> AD<12> AD<11> AD<10> AD<9> AD<8> AD<7> AD<6> AD<5> AD<4> AD<3> AD<2> AD<1> AD<0> C/BE<3> C/BE<2> C/BE<1> C/BE<0> P_ENUMB P_PAR P_DEVSELB P_STOPB P_SERRB P_PERRB P_LOCKB P_FRAMEB P_TRDYB P_IRDYB P_IDSEL P_REQB P_RSTB P_GNTB P_CLK P_INTAB
10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10
39.2
2 3 4 1 2 3 4 3 4 1 2 3 4 1 2 2 3 4 1 2 3 4 1 2 4 1 2 3 4 1 2 3 1 3 1 3 4 4 3 4 3 2 1 4 2 1 2 1
7 6 5 8 7 6 5 6 5 8 7 6 5 8 7 7 6 5 8 7 6 5 8 7 5 8 7 6 5 8 7 6 8 6 8 6 5 5 6 5 6 7 8 5 7 8 7 8
RN8_1 RN8_1 RN8_1 RN9_1 RN9_1 RN9_1 RN9_1 RN10_1 RN10_1 RN11_1 RN11_1 RN11_1 RN11_1 RN12_1 RN12_1 RN17_1 RN17_1 RN17_1 RN18_1 RN18_1 RN18_1 RN18_1 RN19_1 RN19_1 RN19_1 RN20_1 RN20_1 RN20_1 RN20_1 RN21_1 RN21_1 RN21_1 RN10_1 RN12_1 RN17_1 RN19_1 RN21_1 RN14_1 RN13_1 RN13_1 RN14_1 RN14_1 RN14_1 RN12_1 RN13_1 RN13_1 RN10_1
R16_1
ADX31 ADX30 ADX29 ADX28 ADX27 ADX26 ADX25 ADX24 ADX23 ADX22 ADX21 ADX20 ADX19 ADX18 ADX17 ADX16 ADX15 ADX14 ADX13 ADX12 ADX11 ADX10 ADX9 ADX8 ADX7 ADX6 ADX5 ADX4 ADX3 ADX2 ADX1 ADX0 CBEX3 CBEX2 CBEX1 CBEX0 ENUMX PARX DEVSELX STOPX SERRX PERRX LOCKX FRAMEX TRDYX IRDYX IDSELX REQX
173 174 175 2 3 4 5 8 9 10 11 12 13 14 15 31 32 33 34 36 37 38 39 40 42 43 46 47 48 49 50 51 6 16 30 41 167 52 29 22 23 26 25 24 17 21 18 7 172 169 171 170 168
AD<31> AD<30> AD<29> AD<28> AD<27> AD<26> AD<25> AD<24> AD<23> AD<22> AD<21> AD<20> AD<19> AD<18> AD<17> AD<16> AD<15> AD<14> AD<13> AD<12> AD<11> AD<10> AD<9> AD<8> AD<7> AD<6> AD<5> AD<4> AD<3> AD<2> AD<1> AD<0>
VDD15 VDD14 VDD13 VDD12 VDD11 VDD10 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 DP<3> DP<2> DP<1> DP<0>
5 6 5 8
4.7K 4.7K 4.7K 4.7K RN4_1 RN5_1 RN5_1 RN4_1
4 3 4 1
RES_ARRAY_4
2 3 4 1
3 1 3 2
2 4 1 4
RN2_1 RN2_1 RN2_1 RN1_1
RN1_1 RN5_1 RN3_1 RN3_1
RN1_1 RN3_1 RN2_1 RN1_1
RN4_1 RN3_1 RN5_1 RN4_1
3 1 2 2
G
PART#PCI9054-AB50PI
U2_1
BTERM* BIGEND* LHOLDA LHOLD BLAST* LW/R* BREQO READY* LSERR* ADS* LBE2* LBE3* DMPAF/EOT* WAIT* BREQI CCS* LCLK LEDON/LEDIN LINT* LRESETO* USERI/DACK0/LLOCKI* USERO/DREQ0/LLOCKO* MODE<1> MODE<0> TEST VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1
LHOLDA\I LHOLD\I L_WRB\I L_READYB\I L_ADSB\I
13E7<
13D7> 13D7<
F
13D7> 13E7<
PCI9054 C-MODE
C/BE<3>* C/BE<2>* C/BE<1>* C/BE<0>* PME* ENUM* PAR DEVSEL* STOP* SERR* PERR* LOCK* FRAME* TRDY* IRDY* IDSEL REQ* RST* GNT* PCLK INTA* EEDI/O EESK EECS
15C5< 15C5<> 15F5<> 15C5<> 15F5< 15A5<>
L_CLK\I L_INTB\I L_RSTOB\I L_USERI\I L_USERO\I
13E7> 13E1> 13C10< 13E1> 13E7<
E
1 1K 2 1K 3 1K 4 1K
15B5> 15C5> 15G5<
10
1
8
RN7_1
INTAX RSTX 3.3 V
5
LBE0* LBE1* LA<2> LA<3> LA<4> LA<5> LA<6> LA<7> LA<8> LA<9> LA<10> LA<11> LA<12> LA<13> LA<14> LA<15> LA<16> LA<17> LA<18> LA<19> LA<20> LA<21> LA<22> LA<23> LA<24> LA<25> LA<26> LA<27> LA<28> LA<29> LA<30> LA<31>
8 7 6 5
2
B A
VCC
RN15_1 RN15_1 RN15_1 RN15_1
RN6_1 RN6_1 RN6_1 RN6_1
U14
16D8>
8 7 6 5
1 1K 2 1K 3 1K 4 1K
15B5<> 15E5<> 15B5<> 15D5<> 15E5> 15G5< 15D5>
10
RN8_1
LBE0 LBE1
E
LBE0 94 LBE1 93
PWROK_1_8V\I
1
GND
3
D
166 165 164
87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 68 67 66 65 64 63 60 59 58 57 56 55 54
OUT
4
3.3 V D
0.1UF C16_1 0.1UF C17_1 0.1UF C15_1 0.1UF 0.1UF C14_1 0.1UF C19_1 0.1UF C22_1 0.1UF C13_1 C23_1 10UF C24_1 10UF
LA<31..2>\I
3.3 V
3.3 V
5E9< 10F8<
13G1<
13G10<
C20_1 0.1UF
C21_1
R14_1
10UF
4.7K
+
U1_1
NM93CS66LEN
PLACE AROUND U2
1 2 3 4 2.2K R13_1
C PLACE NEAR U1
4.7K
R15_1
8 7 6 5
VCC PRE PE GND
CS SK DI DO
C25_1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
+
+
C
PRECHARGE
D1_1
DL4148
ADJ U3_1
LT1117CST
1V_PRECHG 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K
1
2
2 4 R12_1 150
VIN VOUT TAB ADJ
3
3_3V_LONG
15H7>
VIO_LONG
15H7>
0.1UF
R11_1
C4_1
1
R10_1
8
5
8
100
7
10K 10K 10K 10K
6
7
8
5
6
7
8
5
7
8
5
6
7
8
5
6
7
7
8
5
6
7
8
5
6
5
6
7
8
5
6
7
6
8
6
8
5
8
7
6
5
7
8
5
7
6
24
100K
R8_1
3
2
1
4
3
2
1
4
2
1
4
3
2
1
4
3
2
2
1
4
3
2
1
4
3
4
3
2
1
4
3
2
3
1
3
1
4
1
2
3
4
2
1
4
2
RN22_1 RN22_1 RN22_1 RN23_1 RN23_1 RN23_1 RN23_1 RN24_1 RN24_1 RN24_1 RN25_1 RN25_1 RN25_1 RN25_1 RN26_1 RN26_1 RN26_1 RN30_1 RN30_1 RN31_1 RN31_1 RN31_1 RN31_1 RN32_1 RN32_1 RN33_1 RN33_1 RN33_1 RN33_1 RN34_1 RN34_1 RN34_1
RN24_1 RN26_1 RN30_1 RN32_1 RN30_1 RN29_1 RN29_1 RN29_1 RN29_1 RN32_1 RN28_1 RN28_1 RN28_1 RN28_1
3
B
B
1
4
1
RN34_1 RN22_1 RN27_1 RN27_1
2
CBEX0 CBEX1 CBEX2 CBEX3 FRAMEX IRDYX TRDYX DEVSELX STOPX IDSELX LOCKX PARX PERRX SERRX
DRAWING: TITLE=CPCI_BLOCK ABBREV=CPCI_BLOCK LAST_MODIFIED=Thu Jun 15 10:02:12 2000 P_GNTB
ADX0 ADX1 ADX2 ADX3 ADX4 ADX5 ADX6 ADX7 ADX8 ADX9 ADX10 ADX11 ADX12 ADX13 ADX14 ADX15 ADX16 ADX17 ADX18 ADX19 ADX20 ADX21 ADX22 ADX23 ADX24 ADX25 ADX26 ADX27 ADX28 ADX29 ADX30 ADX31
RSTX ENUMX INTAX REQX
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-991413 DOCUMENT ISSUE NUMBER: 1 TITLE: CPCI_BLOCK CPCI_BLOCK ENGINEER: PMC 2 ISSUE DATE: YY/MM/DD REVISION NUMBER: 2 PAGE:N 1 OF M A
A
NOTES: 1. 2. 3. 4. 5.
ALL 10 OHM STUBS WITHIN 0.6" ALL PCI SIGNAL TRACES < 1.5" P_CLK TRACE MUST BE 2.5" +/CPCI BUS TRACES ARE 65 OHM. 39 OHM STUB RESISTOR ON REQB
OF J1 EXCEPT P_CLK 0.1" PLACED NEAR BRIDGE PIN
10
9
8
7
6
5
4
3
10
9
8
7
6
5
4
3
2
1
REVISIONS
AD<31..0>
14H10<>
ZONE
REV
DESCRIPTION
DATE
APPR
H C/BE<3..0>
14F10<>
H 3.3 V
16F8<
16G8<
14C5<
14C3<
16F8<
1 2 3 4
4.7K 4.7K 4.7K 4.7K
3_3V_PCI\I
5V_PCI\I
3_3V_LONG
VIO_LONG
RN16_1 8 RN16_1 7 RN16_1 6 RN16_1 5
CPCI J1
G
J1_1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 ZPACK5X22A CPCI
A1 A2 A3 A4 A5 A6 A7 AD<30> A8 AD<26> A9 C/BE<3> A10 AD<21> A11 AD<18> A15 A16 A17 A18 A19 A20 AD<12> A21 A22 AD<7> A23 A24 AD<1> A25 B1 B2 B3 B4 B5 B6 B7 AD<29> B8 B9 B10 B11 AD<17> B15 B16 B17 B18 B19 AD<15> B20 B21 AD<9> B22 B23 AD<4> B24 B25 C1 C2 C3 C4 C5 C6 C7 AD<28> C8 C9 AD<23> C10 C11 AD<16> C15 C16 C17 C18 C19 AD<14> C20 C21 AD<8> C22 C23 AD<3> C24 C25 D1 D2 D3 D4 D5 D6 D7 D8 AD<25> D9 D10 AD<20> D11 D15 D16 D17 D18 D19 D20 AD<11> D21 D22 AD<6> D23 D24 AD<0> D25 E1 E2 E3 E4 E5 E6 AD<31> E7 AD<27> E8 AD<24> E9 AD<22> E10 AD<19> E11 C/BE<2> E15 E16 E17 E18 C/BE<1> E19 AD<13> E20 AD<10> E21 C/BE<0> E22 AD<5> E23 AD<2> E24 E25
VIO_PCI\I
PLACE DECOUPLING CAPS CLOSE TO CONNECTOR 5V_PCI\I
0.1UF C10_1 10UF
3_3V_PCI\I
0.1UF C5_1 0.1UF C12_1 10UF
VIO_PCI\I
0.1UF C9_1 10UF C11_1 10UF C8_1
C6_1
+
+
+
C7_1
+
G
P_INTAB P_REQB
30 26 3 21 18
14E9> 14E9>
10 R? 0.1UF 0.1UF C18_1 10UF
12V_PCI\I P_DEVSELB P_SERRB
14E9<> 14E9>
VEE_PCI\I
C1_1 10UF
C3_1
+
F
F1 F3 F5 F7 F9 F11 F13 F15 F17 F19 F21 F23 F25
F1 F3 F5 F7 F9 F11 F13 F15 F17 F19 F21 F23 F25
12 7 1
C2_1
+
F
VEE_PCI\I HEALTHYB\I
29
16E8< 16E8>
P_IDSEL
17
14E9< 14E9<>
P_FRAMEB
E
15 9 4
E
P_RSTB
28
P1_1
14E9<
STRIP3
23 16
3
1
10M 2 R2_1
HOLE_SIZE= 150 MIL
MOUNTING HOLE
D
P_IRDYB
STRIP2
14E9<>
ESD STRIP
10M R3_1
TP2_1 T CHASSIS D TP1_1 T CHASSIS
14 8 3
STRIP1
CPCI ESD STRIP
1 R1_1
P_ENUMB 12V_PCI\I
14E9> 16E8<
P_CLK
25 20
14E9<
C
10M
C
BD_SELB\I P_STOPB P_PAR
11 6 0
16E8< 14E9<> 14E9<>
B
B P_GNTB
31 27 24 22 19 2
14E9<
P_TRDYB P_LOCKB P_PERRB
1 13 10 0 5 2
14E9<> 14E9<> 14E9<>
DRAWING: TITLE=CPCI_BLOCK ABBREV=CPCI_BLOCK LAST_MODIFIED=Thu Jun 15 10:02:16 2000
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-991245 DOCUMENT ISSUE NUMBER: 1 TITLE: SPECTRA 4X155 REFERENCE DESIGN CPCI_BLOCK ENGINEER: MB 2 ISSUE DATE: YY/MM/DD REVISION NUMBER: 2 PAGE:15 1 OF 16 A
A
10
9
8
7
6
5
4
3
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
10
BILL OF MATERIAL
Table 3
Item Ref. No
- Bill of Material
Description Manufactures Part #
1 U6
IC QUAD 2 IN AND GATE SOIC14 NARROW BODY 2 J5, J6 Z-PACK 6 ROW HS3 BACKPLANE CONNECTOR, RIGHT ANGLE RECEPTACLE 3 C67-C78, C7_2 CAP CERAMIC X7R 0603 50V 0.01UF 4 C8_2 CAP CERAMIC X7R 1206 50V 0.047UF 5 C10_1, C3, C6, CAP CERAMIC X7R 0603 16V C7, C13-C20, C35, 0.1UF C36, C39, C44, C51, C63-C66, C80-C84, C88C119, C11_1, C120-C129, C12_1, C130, C131, C133-C139, C13_1, C140C149, C14_1, C150-C159, C15_1, C160C169, C16_1, C170-C177, C17_1, C18_1, C19_1, C1_1, C21_1, C22_1, C23_1, C4_1, C5_2, C6_2, C9_1 6 C79, C85-C87 CAP SERAMIC X7R 0805 16V 0.22UF 7 C1, C2, C20_1, CAP TANCAPC 16V 20% 10UF C24_1, C25_1, C29, C2_1, C4, C5, C8, C9, C30C34, C37, C38, C3_1, C40-C43,
MM74HC08M 120673-1 ECU-V1H103KBV ECU-V1H473KBW ECJ-1VB1C104K
ECJ-1VB1C224K ECS-H1CC106R
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
21
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
Item
Ref. No
Description
Manufactures Part #
C45-C49, C52C55, C57-C59, C5_1, C60-C62, C6_1, C7_1, C8_1 8 C2_2, C3_2 CAP TANCAPC 35V 20% 2.2UF ECS-H1VC225R 9 C1_2, C4_2, C9_2 CAP ELECTRO VA SMD 10V 20% ECE-V1AA221P 220UF 10 C10-C12, C21CAP TANCAPD 10V 20% 47UF ECS-H1AD476R C28, C56 11 J14 38 PIN SIGNAL CONNECTOR, 2-767004-2 MATCHED IMPEDANCE, 0.025, SMD 12 P1_1 COMPACT PCI ESD STRIP, PART OF PCB CREATE ON PCB LAYOUT 13 D1_1 DIODE RECT 150MA 75V SMT DL4148MS MINIMELF 14 J11 CONN HEADER STRAIGHT PZC36SAAN 36POS MALE .1" SINGLE ROW 15 J4 CONN HEADER STRAIGHT PZC36SAAN 36POS MALE .1" SINGLE ROW 16 J13 CONN HEADER STRAIGHT PZC36SAAN 36POS MALE .1" SINGLE ROW 17 J7, J12 CONN HEADER STRAIGHT PZC36SAAN 36POS MALE .1" SINGLE ROW 18 J8, J9 CONN HEADER STRAIGHT PZC36SAAN 36POS MALE .1" SINGLE ROW 19 J15 50 MIL SPACING HEADER (150 SAMTEC HTMSPOS PER PART) 150-25-G-S-1 25 20 J10 HEADER 2X4 SMT 2MM MALE 87267-0850 21 J2 CONNECTOR HEADER 6X2 .1" PZC36DAAN 22 U1-U4 MT-RJ DUPLEX SINGLE MODE HFCT-5905E TRANSCEIVER HFCT-5905E 23 L1-L8 1.81 DIGI-KEY -PCD1172CT-ND 24 Q1_2, Q2_2 IC MOSFET POWER IRF7413 25 U7 REGULATOR VARIABLE LM1085 MICROPOWER LOW DROPOUT 3.3V 26 U12 REGULATOR VARIABLE LM1085IS-ADJ MICROPOWER LOW DROPOUT ADJUSTABLE 27 U3_1 REGULATOR ADJUSTABLE LT1117CST SOT223 800MA OUTPUT
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
22
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
Item
Ref. No
Description
Manufactures Part #
28 U2_2 29 U5 30 U3_2 31 Y1 32 Y2 33 U13 34 U8
35 M1_1 36 U1_1 37 SW1 38 U2_1 39 U10 40 R14_2, R15_2, R5_2 41 R67, R70 42 R2_2 43 R6_2, R8_2 44 R10, R10_1, R4, R7, R13, R29, R31, R32, R64, R9_2 45 R16_2, R8_1 46 R1_1, R2_1, R3_1 47 R12_1 48 R10_2, R50-R61 49 R1_2 50 R3_2, R4_2 51 R13_1
IC CPCI HOT SWAP CONTROLLER 4 PIN UP VOLTAGE MONITOR WITH MANUAL RESET INPUT 3.08V SOT143 IC VOLTAGE MONITOR WITH MANUAL RESET INPUT 2.63V SOT143 OSC HCMOS/TTL HALF SIZE 8 PIN 19.44MHZ 20PPM OSC HCMOS/TTL HALF SIZE 8 PIN 77.76MHZ 100PPM IC DUAL DIFFERENTIAL LVPECL TO TTL TRANSLATOR SOIC8 IC OCTAL 3-STATE NONINVERTING BUFFER/LINE DRIVER/LINE RECEIVER SO20WB MOUNTING HOLE .150" DIA 4096 BIT SERIAL EEPROM W/ DATA PROTECT AND SEQ READ DIP8 VERT PCB MOUNT SPST PUSH BUTTOM IC PCI-TO-LOCAL BUS IC 3.3V 2X1:5 CMOS CLOCK DRIVER QSOP20 RES 2512 1W 1% 0.01 OHM RES 0603 1/16W RES 0603 1/16W RES 0603 1/16W RES 0603 1/16W 5% 1.0K OHM 5% 1.2K OHM 5% 10 OHM 1% 100 OHM
LTC1643LCGN MAX811TEUS-T MAX812REUS-T MB3020H4819.44MH Z MB3100H77.76MHZ MC100LVELT23D MC74HC244ADW
MOUNTING HOLE NM93CS66LEN DIGIKEY -P8009S-ND PCI9054-AB50PI PI49FCT3805CQ WSL2512-R01-1 ERJ-3GSYJ102V ERJ-3GSYJ122V ERJ-3GSYJ100V ERJ-3EKF1000V
RES 0603 1/16W 5% 100K OHM RES 1206 1/8W 5% 10M OHM RES 0603 1/16W 1% 150 OHM RES 0603 1/16W 5% 150 OHM RES 0603 1/16W 1% 182 OHM RES 0603 1/16W 5% 2.0K OHM RES 0603 1/16W 5% 2.2K OHM
ERJ-3GSYJ104V ERJ-8GEYJ106V ERJ-3EKF1500V ERJ-3GSYJ151V ERJ-3EKF1820V ERJ-3GSYJ202V ERJ-3GSYJ222V
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
23
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
Item
Ref. No
Description
Manufactures Part #
52 R1, R33 53 R35, R37, R39, R41 54 R11_1 55 R69 56 R34, R36, R38, R40 57 R16_1 58 R14_1, R20-R25, R62, R65, R66, R68, R7_1, R7_2 59 R42-R49 60 R26-R28, R63 61 R12_2, R13_2 62 R11_2 63 RN10_1, RN11_1, RN12_1, RN13_1, RN14_1, RN17_1, RN18_1, RN19_1, RN20_1, RN21_1, RN7_1, RN8_1, RN9_1 64 RN22_1, RN23_1, RN24_1, RN25_1, RN26_1, RN27_1, RN28_1, RN29_1, RN30_1, RN31_1, RN32_1, RN33_1, RN34_1 65 RN15_1, RN6_1 66 RN3-RN16, RN16_1, RN17RN19, RN1_1, RN20-RN25, RN27-RN29, RN2_1, RN30RN34, RN3_1, RN4_1, RN5_1 67 RN26 68 U1_2
RES 0805 1/10W 1% 2.7 OHM RES 0603 1/16W 5% 220 OHM RES 0805 1/10W 5% 24 OHM RES 0603 1/16W 1% 3.16K OHM RES 0603 1/16W 5% 330 OHM RES 0603 1/16W 1% 39.2 OHM RES 0603 1/16W 5% 4.7K OHM RES 0603 1/16W RES 0603 1/16W RES 0603 1/16W RES 0603 1/16W 1% 49.9 OHM 5% 56 OHM 5% 560 OHM 1% 63.4 OHM
ERJ-6RQF2R7V ERJ-3GSYJ221V ERJ-6GEYJ240V ERJ-3EKF3161V ERJ-3GSYJ331V ERJ-3EKF39R2V ERJ-3GSYJ472V ERJ-3EKF49R9V ERJ-3GSYJ560V ERJ-3GSYJ561V ERJ-3EKF63R4V PANASONIC -EXB-V8V100JV
PANASONIC -EXB-V8V103JV
PANASONIC -EXB-V8V102JV PANASONIC -EXB-V8V472JV
PANASONIC -EXB-V8V560JV IC REGULATOR 3.3V TO 1.8V 20 SIE501.8R WATTS
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
24
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
Item
Ref. No
Description
Manufactures Part #
69 J1, J3 70 U9 71 D2_2 72 D2 73 D1 74 U15 75 TP1_1, TP2_1 76 U11 77 D1_2 78 J1_1 79 U14
SMB VERTICAL GOLD MONOLITHIC FOUR CHANNEL SONET/SDH PAYLOAD EXTRACTOR/ALIGNER LED QUAD GREEN HORIZONTAL LED QUAD RED HORIZONTAL LED QUAD YELLOW HORIZONTAL TELECOMBUS SERIALIZER CONNECTOR HEADER STRAIGHT SINGLE .1" CPLD 3.3V 10NS
ARF1244-ND PM5316 SSF-LXH5147LGD SSF-LXH5147LID SSF-LXH5147LYD PM5310 N/A
XC9572XL10TQ100I DIGI-KEY ZM4742ACT-ND CONNECTOR ZPACK CPCI 2MM 352068-1 HM 110 POS. TYPE A WITH GND SHIELD IC SINGLE 2-INPUT POSITIVE SN74AHC1G08DC AND GATE KR
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
25
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
NOTES
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
26
PRELIMINARY REFERENCE DESIGN PMC-1991245 ISSUE 1
PM5316/PM5310
SPECTRA-4X155 WITH TBS REFERENCE DESIGN
CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2000 PMC-Sierra, Inc. PMC-1991245 (P1) Issue date: March 2000
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE

▲Up To Search▲

Price & Availability of 1991245

	To Download 1991245 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .